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Publikováno v:
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03.
In this paper, a method to partition a CMOS analog circuit to extract symmetrical layout constraints of the circuit is presented. We implement it as a program that will be apart of an automatic analog circuit layout constraints extraction tool. To fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75d8d6747ffb9556c66efe63f599bd5c
https://doi.org/10.1109/icasic.2003.1277515
https://doi.org/10.1109/icasic.2003.1277515
