Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Steven M. Baier"'
Autor:
Steven M. Baier, David E. Fulkerson
Publikováno v:
Solid-State Electronics. 43:65-71
N-channel transistors are described with gate lengths of 0.6 and 0.3 μm using complementary heterostructure FET (CHFET) technology. The drain current vs gate voltage curves fit a theoretical equation that includes effective mobility, peak electron v
Publikováno v:
Solid-State Electronics. 39:461-469
A quantitative comparison is given between complementary heterostructure FET (CHFET) and silicon-on-insulator (SOI) complementary logic gates. Using the same power supply (1.3 V), the same gate length (0.7 μm), and the same gate capacitance for the
Publikováno v:
IEEE Transactions on Electron Devices. 43:201-206
The high temperature performance of Al/sub 0.75/Ga/sub 0.25/As/In/sub 0.25/Ga/sub 0.75/As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between 25 and 500/spl deg/C. Both experimental and modeled devices have shown acceptable digital ch
Publikováno v:
Materials Science and Engineering: B. 29:54-57
A complementary III–V heterostructure field effect transistor (CHFET) has been developed which employs a high aluminium mole fraction aluminium gallium arsenide (Al 0.75 GaAs) interfacial layer between the gate metallization and the indium gallium
Publikováno v:
IEEE Transactions on Electron Devices. 41:888-894
This paper discusses a characterization at 4 K of the complementary heterojunction field-effect transistor (CHFET), to examine its suitability for deep cryogenic ( >
Publikováno v:
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611).
In this paper, we present an efficient approach to the modeling and simulation of mixed-domain electrical/optical systems utilizing a single kernel simulator. The approach is illustrated by a case study of an optoelectronic interconnect system.
Publikováno v:
IEEE Electron Device Letters. 13:645-647
The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFETs) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, therm
Publikováno v:
SPIE Proceedings.
This paper discusses the lates results of a continuing study of the properties of the complementary heterojunction field-effect transistor (CHFET) at 4K. The electrical characteristics, including the gate leakage current and the subthreshold transcon
Autor:
Steven M. Baier, Jim Nohava, B. Grung, A. Fraasch-Vold, Richard G. Schulze, J.J. Stronczer, D.E. Grider
Publikováno v:
SPIE Proceedings.
This paper describes a CMOS-like readout technology using GaAs heterostructure field effect transistors. Bandgapengineering techniques are described which provide complementaiy p-channel and n-channel GaAs FETs attractive forperforming advanced signa
Publikováno v:
SPIE Proceedings.
Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the tra