Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Steven D. Pyle"'
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 5, Iss 1, Pp 43-51 (2019)
The neural sampling core (NSC) proposed herein offers a spintronic device-based circuit and learning mechanism utilizing imprecise and stochastic components, similar to biological brains, to realize ultralow-power neuromorphic computations at subthre
Externí odkaz:
https://doaj.org/article/bb8c8371ed284c7eaf5eb84bd3acc570
Publikováno v:
IET Computers & Digital Techniques. 12:122-129
The spintronic stochastic spiking neuron (S3N) developed herein realises biologically mimetic stochastic spiking characteristics observed within in vivo cortical neurons, while operating several orders of magnitude more rapidly and exhibiting a favou
Publikováno v:
IEEE Transactions on Magnetics. 54:1-7
The complementary roles of asynchronous architecture with nonvolatile spintronic devices are explored herein to realize a novel asynchronous logic element. By redesigning the Muller C-element to take advantage of spintronic device non-volatility and
Publikováno v:
MWSCAS
State-of-the-art machine learning models have achieved impressive feats of narrow intelligence, but have yet to realize the computational generality, adaptability, and power efficiency of biological brains. Thus, this work aims to improve current neu
Publikováno v:
2019 IEEE Integrated STEM Education Conference (ISEC).
Inspired by the success of Computer-Based Assessment (CBA) prevalent in disciplines outside of Engineering, a large-scale multiple-year project has been undertaken at the University of Central Florida (UCF) to develop authentic CBA assessments. To-da
Autor:
Steven D. Pyle, Ronald F. DeMara
Publikováno v:
SoutheastCon 2018.
A prominent issue with spintronic architectures is the requirement to use charge current in order to realize magnetic state transduction, and thus, device concatenation, which is far less efficient than voltage-based devices, such as CMOS. With the a
Compact low‐power instant store and restore D flip‐flop using a self‐complementing spintronic device
Publikováno v:
Electronics Letters. 52:1238-1240
To simplify power-gating requirements in ultra-low-power architectures, design strategies for low-power non-volatile flip-flops (F/Fs) are sought, for which the utilisation of spintronic devices offers a promising option. A D F/F that utilises a five
Publikováno v:
ICRC
The architecture, operation, and characteristics of two post-CMOS reconfigurable fabrics are identified to realize energy-sparing and resilience features, while remaining feasible for near-term fabrication. First, Storage Cell Replacement Fabrics (SC
A low-energy hardware implementation of deep belief network (DBN) architecture is developed using near-zero energy barrier probabilistic spin logic devices (p-bits), which are modeled to realize an intrinsic sigmoidal activation function. A CMOS/spin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ace5dd356ec933ac54d886306e632902
http://arxiv.org/abs/1710.00249
http://arxiv.org/abs/1710.00249
Publikováno v:
AHS
We introduce SCALER, a two-pronged strategy utilizing digital resources for refining intrinsic evolution of analog computational circuits. A Self-Scaling Genetic Algorithm is proposed to adapt solutions to computationally-tractable ranges in hardware