Zobrazeno 1 - 10
of 39
pro vyhledávání: '"Steve Dai"'
Autor:
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:1129-1141
Autor:
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
Steve Dai, Ben Keller, William J. Dally, Brucek Khailany, Rangharajan Venkatesan, Alicia Klinefelter, Robert M. Kirby, Saad Godil, Yanqing Zhang, Haoxing Ren, Bryan Catanzaro
Publikováno v:
IEEE Micro. 40:23-32
Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic desi
Autor:
Ian Galton, Ritchie Zhao, Tutu Ajayi, Shaolin Xie, Christopher Batten, Paul Gao, Austin Rovinski, Chun Zhao, Steve Dai, Scott Davidson, Dustin Richmond, Aporva Amarnath, Zhiru Zhang, Khalid Al-Hawaj, Ronald G. Dreslinski, Luis Vega, Bandhav Veluri, Anuj Rao, Julian Puscar, Michael Taylor, Christopher Torng
Publikováno v:
IEEE Solid-State Circuits Letters. 2:289-292
This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark b
Publikováno v:
Journal of the American Ceramic Society. 102:5180-5191
Publikováno v:
DAC
Transformers have transformed the field of natural language processing. This performance is largely attributed to the use of stacked self-attention layers, each of which consists of matrix multiplies as well as softmax operations. As a result, unlike
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a43f355bec7dd1e3998c35892316aab8
http://arxiv.org/abs/2103.09301
http://arxiv.org/abs/2103.09301
Publikováno v:
FPGA
FCCM
FCCM
Image processing applications can benefit tremendously from FPGA acceleration. However, hardware accelerators for these applications look very different from the programs that image processing algorithm designers are accustomed to writing. As a resul
Autor:
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar
Representing deep neural networks (DNNs) in low-precision is a promising approach to enable efficient acceleration and memory reduction. Previous methods that train DNNs in low-precision typically keep a copy of weights in high-precision during the w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::96561221c389ff836eb77e2054e9f381
Autor:
Miaorong Wang, Nathaniel Pinckney, Brucek Khailany, Alicia Klinefelter, Rangharajan Venkatesan, Ben Keller, Jason Clemons, William J. Dally, Matthew Fojtik, Stephen W. Keckler, Brian Zimmer, Yakun Sophia Shao, Joel Emer, Priyanka Raina, Yanqing Zhang, Steve Dai
Publikováno v:
ICCAD
Deep neural networks have been adopted in a wide range of application domains, leading to high demand for inference accelerators. However, the high cost associated with ASIC hardware design makes it challenging to build custom accelerators for differ
Autor:
Michael Taylor, Anuj Rao, Christopher Torng, Zhiru Zhang, Khalid Al-Hawai, Ritchie Zhao, Austin Rovinski, Shaolin Xie, Steve Dai, Aporva Amarnath, Ronald G. Dreslinski, Rajesh Gupta, Tutu Ajayi, Luis Vega, Scott Davidson, Bandhav Veluri, Gai Liu, Chun Zhao, Christopher Batten, Paul Gao
Publikováno v:
IEEE Micro. 38:30-41
Rapidly emerging workloads require rapidly developed chips. The Celerity 16-nm open-source SoC was implemented in nine months using an architectural trifecta to minimize development time: a general-purpose tier comprised of open-source Linux-capable