Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Stephen S. Furkay"'
Autor:
Philip J. Oldiges, Mohit Bajaj, Kota V. R. M. Murali, Robert R. Robison, Jeffrey B. Johnson, Samarth Agarwal, Stephen S. Furkay
Publikováno v:
Journal of Computational Electronics. 14:533-536
A hybrid approach to model the effect of random dopant fluctuations in low doped FinFETs is proposed. Existing Monte Carlo and atomistic approaches are found to be inadequate to capture device variability correctly when applied independently. Instead
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa566c731f73f0b695c7069f5e1f5070
https://doi.org/10.1007/s10825-015-0684-2
https://doi.org/10.1007/s10825-015-0684-2
Autor:
Kota V. R. M. Murali, Phil Oldiges, Mohit Bajaj, Kai Xiu, Samarth Agarwal, Jeffrey B. Johnson, Stephen S. Furkay
Publikováno v:
Journal of Computational Electronics. 14:163-166
Using a finite element based treatment, the Schrodinger equation is solved in 3D for non-planer devices like FinFETs. Discrete states appearing because of three dimensional geometric and electrostatic confinement in a FinFET are used to calculate the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c632c958150c165a4e2fc4e275c3b4ed
https://doi.org/10.1007/s10825-014-0610-z
https://doi.org/10.1007/s10825-014-0610-z
Autor:
Puneet Goyal, Kota V. R. M. Murali, Rishikesh Krishnan, Ninad D. Sathaye, Subramanian S. Iyer, Sandip De, Edward J. Nowak, Balaji Jayaraman, Stephen S. Furkay, Rajan K. Pandey, Mohit Bajaj
Publikováno v:
IEEE Transactions on Electron Devices. 60:4152-4158
We report experimental characterization and modeling of direct and trap-assisted tunneling (TAT) in high-K metal gate (HKMG)-based access transistor and deep trench (DT) capacitor constituting a 32 nm embedded dynamic random access memory (eDRAM) dev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8c4127c94185bf4b9fcec230fe7d761
https://doi.org/10.1109/ted.2013.2285940
https://doi.org/10.1109/ted.2013.2285940
Autor:
Mohit Bajaj, Samarth Agarwal, Abhisek Dixit, Jeffrey B. Johnson, Kota V. R. M. Murali, Stephen S. Furkay, Phil Oldiges, Rajan K. Pandey
Publikováno v:
IEEE Transactions on Electron Devices. 60:2728-2733
A novel method to model the effect of local workfunction variation in high-k metal gate nanoscale transistors is proposed. Impact of variability in metal grain granularity on device performance is studied using ab initio density functional theory cal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56be4377511b9b37b1a8573a7e513b07
https://doi.org/10.1109/ted.2013.2272998
https://doi.org/10.1109/ted.2013.2272998
Publikováno v:
IEEE Transactions on Electron Devices. 57:2098-2105
The efficient and successful realization of low-power semiconductor devices demands, among other things, the ability to quantitatively model and minimize myriad leakage phenomena. We report herein a general physical model to quantitatively compute cr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a1df168daa927fb23eae78d2e79cd35
https://doi.org/10.1109/ted.2010.2054455
https://doi.org/10.1109/ted.2010.2054455
Autor:
M. I. Younus, Michael J. Hauser, Rebecca D. Mih, D. Hoyniak, J. M. Johnson, Matthew J. Breitwisch, W. G. Crocco, Peter E. Cottrell, Wagdi W. Abadeer, A. Moriwaki, Terence B. Hook, E. Phipps, J. Rivard, Orest Bula, Beth Ann Rainey, Randy W. Mann, Jeffrey S. Brown, Christopher S. Putnam, Chung Hon Lam, J. Toomey, Stephen S. Furkay, Bryant C. Colwill
Publikováno v:
IBM Journal of Research and Development. 47:553-566
An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3b323d20dfebe6ad7dd8b0e38b250c6
https://doi.org/10.1147/rd.475.0553
https://doi.org/10.1147/rd.475.0553
Autor:
Basanth Jagannathan, D. Faken, N. Zhan, Manoj Kumar, B. Cipriany, James P. Norum, K. Greiner, S. Breit, Karen A. Nummy, D. Fried, Shreesh Narasimha, B. Zhang, Rajeev Malik, Paul D. Agnello, Gregory Costrini, J. Meiring, Katsunori Onishi, H. Nanjundappa, Ahmed N. Noemaun, Christopher D. Sheraw, Stephen S. Furkay
Publikováno v:
2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
We present a technology development methodology that relies on 3D virtual fabrication to rapidly improve yield by increasing tolerance to multilevel process variation. This methodology has been successfully implemented in the development and yield ra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1abce879f5e1cafa7541e0a6f16ff19
https://doi.org/10.1109/sispad.2013.6650583
https://doi.org/10.1109/sispad.2013.6650583
Three-dimensional transient electrothermal simulation of electrostatic discharge protection circuits
Publikováno v:
Journal of Electrostatics. 36:55-80
Transient electrothermal simulation of ESD protection circuits using the 3-D finite element device simulator will be shown to explain the electrothermal physics in ESD protection circuits in 0.5 and 0.25 μm channel length CMOS technologies. Simulati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76e03cbd9877012692aab3ca73cc6061
https://doi.org/10.1016/0304-3886(95)00024-5
https://doi.org/10.1016/0304-3886(95)00024-5
Publikováno v:
IEEE 2011 International SOI Conference.
We have shown here a comprehensive set of results on the coupling factor in a UTBB technology based on TCAD simulation. An interesting result is the degree to which the coupling factor is not constant across the possible realistic range of biases, an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::970e171b4bfdefc5006193d92cc5b3df
https://doi.org/10.1109/soi.2011.6081684
https://doi.org/10.1109/soi.2011.6081684
Publikováno v:
2011 International Conference on Simulation of Semiconductor Processes and Devices.
A mixed-mode simulation framework is presented to study the AC performance of a 20nm bulk CMOS technology with respect to various options for contact design at the middle-of-line design level. These simulations combine the predictive capabilities of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a704aab5e11ffff5f23c2cb0785aea20
https://doi.org/10.1109/sispad.2011.6035059
https://doi.org/10.1109/sispad.2011.6035059