Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Stephen Maresh"'
Autor:
Dennis Abts, Garrin Kimmell, Andrew Ling, John Kim, Matt Boyd, Andrew Bitar, Sahil Parmar, Ibrahim Ahmed, Roberto DiCecco, David Han, John Thompson, Michael Bye, Jennifer Hwang, Jeremy Fowers, Peter Lillian, Ashwin Murthy, Elyas Mehtabuddin, Chetan Tekur, Thomas Sohmers, Kris Kang, Stephen Maresh, Jonathan Ross
Publikováno v:
Proceedings of the 49th Annual International Symposium on Computer Architecture.
Autor:
Michael Adler, Kermin Fleming, Aamer Jaleel, Antonia Zhai, Rachid Rayess, Tushar Krishna, Joel Emer, Randy Allmon, Vladimir Pavlov, Michael Pellauer, Stephen Maresh, Bushra Ahsan, Neal Crago, Daniel Lustig, Angshuman Parashar, Mohit Gambhir
Publikováno v:
ACM Transactions on Computer Systems. 33:1-32
There has been recent interest in exploring the acceleration of nonvectorizable workloads with spatially programmed architectures that are designed to efficiently exploit pipeline parallelism. Such an architecture faces two main problems: how to effi
Autor:
Joel Emer, Vladimir Pavlov, Bushra Ahsan, Rachid Rayess, Daniel Lustig, Stephen Maresh, Neal Crago, Michael Pellauer, Antonia Zhai, Randy Allmon, Aamer Jaleel, Angshuman Parashar, Mohit Gambhir, Michael Adler
Publikováno v:
IEEE Micro. 34:120-137
In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs
Autor:
Antonia Zhai, Michael Adler, Daniel Lustig, Aamer Jaleel, Neal Crago, Joel Emer, Angshuman Parashar, Stephen Maresh, Randy Allmon, Michael Pellauer, Mohit Gambhir, Vladimir Pavlov, Bushra Ahsan, Rachid Rayess
Publikováno v:
ISCA
In this paper, we present triggered instructions , a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transit
Autor:
B. Munger, V. Kalathur, Stephen Maresh, S. Kovvali, N. O'Neill, R. Hokinson, M. Arneborn, D. Clay, S. Dumford, S. Sayadi, I. Pragaspathy, W. Qin, T. Singh, V. Kalidindi, B. Benschneider, J. Clouser, J. Tang, M. Tracz, R. Sasamori, J. Krause, S. Watkins
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
An Alpha microprocessor design is implemented in a 0.18 /spl mu/m CMOS process, utilizing 7 layers of copper interconnect. Process features include nominal and low Vt transistor options, low-K FSG dielectric and a refractory metal local interconnect