Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Stephen E. Luce"'
Autor:
Micheal Leach, William J. Cote, Stephen E. Luce, Carter Welling Kaanta, William R. Hill, Howard S. Landis, Charles W. Koburger, Cheryl A. Hoffman, Walter Frederick Lange, Peter J Burke
Publikováno v:
Thin Solid Films. 220:1-7
Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1003ff4a79d21c8b67203fc279ce44c8
https://doi.org/10.1016/0040-6090(92)90539-n
https://doi.org/10.1016/0040-6090(92)90539-n
Autor:
B. Porth, Philippe M. Vereecken, Thomas J. Mcdevitt, C. Johnson, Jennifer C. Robbins, T. Rutkowski, M. Wenner, J. Gambino, Erick G. Walton, Stephen E. Luce, Kenneth Lawrence Devries, D. Rath, Jonathan D. Chapple-Sokol
Publikováno v:
2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits.
A new yield loss mechanism is described that is related to the etching of Cu in deionized water. Water that contains high concentrations of dissolved oxygen can etch Cu at the bottom of vias during pre-metallization wet cleans. The etching creates vo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e412f1a769f28f4127f9d445a5c9407
https://doi.org/10.1109/ipfa.2008.4588209
https://doi.org/10.1109/ipfa.2008.4588209
Autor:
William J. Murphy, Daniel S. Vanslette, Stephen E. Luce, Stephen A. Mongeon, Tom C. Lee, Daniel A. Delibac, David C. Thomas, Timothy D. Sullivan, Z.X. He, Jonathan D. Chapple-Sokol
Publikováno v:
MRS Proceedings. 1079
In this paper, we report a novel method to improve aluminum interconnect electromigration performance, reduce metal line sheet resistance (Rs) and reduce via contact resistance (Rc) in a minimum pitch design. We report the effects of bottom redundanc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2a09642561d03146cbcb65d60ea3a8d
https://doi.org/10.1557/proc-1079-n09-01
https://doi.org/10.1557/proc-1079-n09-01
Autor:
V. McGahay, B. Porth, T. Pricer, H. Wildman, C. Benson, C. Senowitz, M. Gibson, A. Piper, Edward C. Cooney, T. Standaert, R. Kontra, A.K. Stamper, Stephen E. Luce, J. Gambino, P. Biolsi, Tom McDevitt
Publikováno v:
Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).
The integration of Cu with low-k dielectrics poses a number of challenges. In this paper, we describe yield issues associated with integration of three different low-k dielectrics; FSG (fluorosilicate glass), OSG (organosilicate glass), and polymers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ece057db322ab70398de5c1dfa6b4660
https://doi.org/10.1109/ipfa.2002.1025628
https://doi.org/10.1109/ipfa.2002.1025628
Autor:
V. Samek, T. Kane, T. Stamper, B. Reuter, Stephen E. Luce, P. McLaughlin, Jeff Gambino, M. Dunbar, H. Trombley, C. Weinstein, F. Allen
Publikováno v:
MRS Proceedings. 766
A trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in suc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f89b59e6334672cd4898b7de61da41cc
https://doi.org/10.1557/proc-766-e5.5
https://doi.org/10.1557/proc-766-e5.5
Autor:
A.K. Stamper, T. Katsetos, P. C. Andricacos, John E. Heidenreich, Stephen E. Luce, John Owen Dukovic, Ronald D. Goldblatt, Naftali E. Lustig, Richard A. Wachnik, J. Slattery, Daniel C. Edelstein, A. Simon, Thomas L. McDevitt, H. S. Rathore, Cyprian E. Uzoh, William J. Cote, P. McLaughlin
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
Recently, IBM announced the implementation of a full copper interconnect scheme which will be manufactured on its high-performance 0.20 /spl mu/m CMOS products later this year. Features of this technology are presented here, as well as functional ver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::847939bd04f73a3e4baee4d7e4937c68
https://doi.org/10.1109/iitc.1998.704776
https://doi.org/10.1109/iitc.1998.704776
Autor:
L. Su, Naftali E. Lustig, John E. Heidenreich, Cyprian E. Uzoh, Peter Roper, Stephen E. Luce, R. Schulz, Richard A. Wachnik, William J. Cote, A. Simon, Ronald D. Goldblatt, J. Dukovic, W. Motsiff, J. Slattery, Daniel C. Edelstein, H. Rathore, Thomas L. McDevitt
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
We present the first fully integrated ULSI CMOS/copper interconnect technology. Up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a polycontacted pitch of 0.81 /spl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::562fb72b2e9b5262a16ac9dec8cab0e7
https://doi.org/10.1109/iedm.1997.650496
https://doi.org/10.1109/iedm.1997.650496
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