Collective Die-to-Wafer Self-Assembly for High Alignment Accuracy and High Throughput 3D Integration

Autor: Alice Bond, Emilie Bourjot, Stephan Borel, Thierry Enot, Pierre Montmeat, Loic Sanchez, Frank Fournel, Johanna Swan

Publikováno v: 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3672e56334867cf5d4dea4db2da01e23
https://doi.org/10.1109/ectc51906.2022.00037

Backside Shield against Physical Attacks for Secure ICs

Autor: Philippe Medina, Romain Wacquez, Eric Jalaguier, Edouard Deschaseaux, Christophe Plantier, Jessy Clédière, Stéphanie Anceau, Gilles Simon, Jacques Fournier, Jean Charbonnier, Stephan Borel

Publikováno v: Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2017:1-15

Although the implementation of multiple countermeasures, both hardware and software, are making integrated circuits more and more secure, the backside of a chip is still considered as a vulnerability regarding physical attacks. A novel protection str

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3162dde956eaa2e6733f2d2c57d2d3a1
https://doi.org/10.4071/2017dpc-wp1_presentation2

A Novel Structure for Backside Protection Against Physical Attacks on Secure Chips or SiP

Autor: Jessy Clédière, Gilles Simon, Edouard Deschaseaux, L. Duperrex, Jean Charbonnier, Jean-Charles Souriau, A. Merle, Stephan Borel, Romain Wacquez, Jacques Fournier

Publikováno v: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. pp.515-520, ⟨10.1109/ECTC.2018.00081⟩

International audience; A structure intended to protect Integrated Circuits (IC) against physical attacks is presented. Located on the backside of a chip, it complements the countermeasures usually available on the front side of secure components. It

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::09a5361672380fd802ea5d4f81fd17e0
https://hal-cea.archives-ouvertes.fr/cea-02185285/document

Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications

Autor: Thierry Chevolleau, Corine Comboroure, S. Pauliac-Vaujeour, Stephan Borel, Jean-Michel Hartmann, Sébastien Barnola, Thomas Ernst, Stéphane Bécu, Bernard Guillaumot, E. Bernard, Christian Arvet, C. Vizioz, Cecilia Dupre, Nathalie Vulliet, V. Maffini-Alvaro, Pauline Gautier

Publikováno v: ECS Transactions. 16:923-934

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isot

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5ed694fd1469cd5ebf6699c533558152
https://doi.org/10.1149/1.2986854

Comparison between three Si1-xGex versus Si selective etching processes

Autor: Stephan Borel, Thierry Salvetat, Jean-Michel Hartmann, Olivier Kermarrec, Yves Campidelli, V Destefanis

Publikováno v: ECS Meeting Abstracts. :2427-2427

Three very different approaches to laterally etch SiGe layers selectively versus Si have been evaluated in terms of etch rate, selectivity and isotropy. The first one calls upon a CF4 plasma at low pressure and room temperature. The second one consis

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2bf684e20476cf1e788946b369786ed6
https://doi.org/10.1149/ma2008-02/37/2427