Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Stepan Harutyunyan"'
Publikováno v:
EWDTS
Over time, the complexity of ICs design increasing which making these designs more error-prone. Verification of Integrated Circuits using Verilog lacks the flexibility and reusability of the environment. System Verilog UVM methodology gives building
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f3881f58f224fef2cee58e0c098a849
https://doi.org/10.1109/ewdts52692.2021.9580997
https://doi.org/10.1109/ewdts52692.2021.9580997
Autor:
Artak Kirakosyan, Stepan Harutyunyan, Vardan Amiryan, Arsen Momjyan, Vazgen Melikyan, Taron Kaplanyan
Publikováno v:
EWDTS
A novel approach of clock domain crossing solution is presented. For high-frequency conditions traditional approach calls for multiple D-flops for single bit synchronization. The higher the frequency the higher the number of flops. In high-frequency
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0781a3773982b393476d528ebc2baa8b
https://doi.org/10.1109/ewdts52692.2021.9580985
https://doi.org/10.1109/ewdts52692.2021.9580985
Publikováno v:
2020 IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO).
Verification of Integrated Circuits using Verilog lacks the flexibility and reusability of the environment. System Verilog provides building blocks and OOP concepts to work with. That allows to create much more flexible test environment with reusable
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a269a2cfa0255168ee3ddccfaa1a4d3
https://doi.org/10.1109/elnano50318.2020.9088878
https://doi.org/10.1109/elnano50318.2020.9088878
Publikováno v:
2020 IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO).
UART is one of the most widely used interfaces. It is as single bit TX and RX interface which supports multiple configurations. It supports data length of 5–8 bits, even, odd or missing parity bit and 3 more stop bit counts. As most UART devices ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8ae81ae02428793e6effadab9e82b6d
https://doi.org/10.1109/elnano50318.2020.9088789
https://doi.org/10.1109/elnano50318.2020.9088789
Autor:
Artur Petrosyan, Mher Bazikyan, Karo Safaryan, Garik Hakobyan, Fadey Aslikyan, Stepan Harutyunyan
Publikováno v:
2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO).
CMOS scaling affects to sub-threshold leakage, gate leakage and device variations growth leakage current. Static Random Access Memory (SRAM) cell is engaged the most area of Integrated Circuit (IC). It has been implemented FinFET bitcell, which leaka
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c3fb247813095872a63c5e19645b12f
https://doi.org/10.1109/elnano.2019.8783371
https://doi.org/10.1109/elnano.2019.8783371
Publikováno v:
2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO).
In applications with high voltage inputs traditional circuits of sense amplifiers can't achieve required speeds. An approach of stable Conventional Voltage Mode Sense Amplifier is presented. Both existing and new approaches have been used to fix the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a26f3b98bc61c2864115fdb39bfc2f7
https://doi.org/10.1109/elnano.2019.8783427
https://doi.org/10.1109/elnano.2019.8783427
Publikováno v:
2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO).
Anapproach of low power XOR gate is presented. Comparison has been done for traditional XOR and XOR heavysystems like binary to gray converter, parity checker. There are significant improvements in power consumption and area with cost of increaseddel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96474e3bbc2e4d8b05e70c0c78456db9
https://doi.org/10.1109/elnano.2019.8783721
https://doi.org/10.1109/elnano.2019.8783721
Publikováno v:
Organometallics. 31:1653-1663
A novel method for the low-temperature generation of Co2(CO)6-complexed propargyl radicals is developed. It consists of an in situ preparation of the respective cationic species (−50 to −10 °C) and their rapid reduction with cobaltocene, Cp2Co,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72d97548096c0c6e652aa43d2124cd6b
https://doi.org/10.1021/om2006497
https://doi.org/10.1021/om2006497