Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Stefan Stattelmann"'
Publikováno v:
Electronic Proceedings in Theoretical Computer Science, Vol 147, Iss Proc. FESCA 2014, Pp 16-31 (2014)
Estimating the execution time of software components is often mandatory when evaluating the non-functional properties of software-intensive systems. This particularly holds for real-time embedded systems, e.g., in the context of industrial automation
Externí odkaz:
https://doaj.org/article/4b3f1103abdf48c5a088eaf7041c221a
Autor:
Thomas Gamer, Stefan Stattelmann
Publikováno v:
atp magazin. 56:42-52
Verfügbarkeit ist in der Automation ein nicht zu vernachlässigender Aspekt bei Design und Betrieb von Systemen. Ausfälle können zu unvorhergesehenen Problemen führen und verursachen meist hohe Kosten. Daher werden Redundanzkonzepte häufig in in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3e88f2118e4da91e1c23c38cdd4839c6
https://doi.org/10.17560/atp.v56i05.2247
https://doi.org/10.17560/atp.v56i05.2247
Publikováno v:
Electronic Proceedings in Theoretical Computer Science, Vol 147, Iss Proc. FESCA 2014, Pp 16-31 (2014)
FESCA
FESCA
Estimating the execution time of software components is often mandatory when evaluating the non-functional properties of software-intensive systems. This particularly holds for real-time embedded systems, e.g., in the context of industrial automation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6072f444e5313012933b4249a4470dc4
https://doaj.org/article/4b3f1103abdf48c5a088eaf7041c221a
https://doaj.org/article/4b3f1103abdf48c5a088eaf7041c221a
Publikováno v:
WODES
This paper presents an efficient static analysis for programmable logic controller code. For each program line (or each function block call), the analysis calculates an over-approximation of the possible values each variable can assume during all pos
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::561c474ef4af7e3f21b495da58734256
https://doi.org/10.3182/20140514-3-fr-4046.00065
https://doi.org/10.3182/20140514-3-fr-4046.00065
Publikováno v:
CASES
We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the mi-croarchitecture state
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ef966b671575e7b10caf60a59637e7e
https://doi.org/10.1145/2656106.2656117
https://doi.org/10.1145/2656106.2656117
Publikováno v:
ETFA
Static code analysis techniques are a well-established tool to improve the efficiency of software developers and for checking the correctness of safety-critical software components. However, their use is often limited to general purpose or “mainstr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b19fd0246cfac2d1ce05de3e1c7cdc19
https://doi.org/10.1109/etfa.2014.7005254
https://doi.org/10.1109/etfa.2014.7005254
Publikováno v:
ETFA
This paper presents optimization techniques for implementing software-based redundancy in industrial control devices. Initially, a brief survey of software-based state replication techniques with a special focus on their applicability in industrial c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96256250534a56e00d24bf0e35ea13a2
https://doi.org/10.1109/etfa.2014.7005112
https://doi.org/10.1109/etfa.2014.7005112
Publikováno v:
Computer Aided Verification ISBN: 9783319088662
CAV
CAV
G4LTL-ST automatically synthesizes control code for industrial Programmable Logic Controls (PLC) from timed behavioral specifications of input-output signals. These specifications are expressed in a linear temporal logic (LTL) extended with non-linea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ee1a4a9a0fd50149bf282b1152d149c
https://doi.org/10.1007/978-3-319-08867-9_36
https://doi.org/10.1007/978-3-319-08867-9_36
Publikováno v:
SIES
Simulation-based approaches to evaluate the functional and non-functional properties of embedded software are in widespread industrial use for design space exploration and virtual prototyping. As simulation performance is usually the main concern for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb66b4d9857e8326f7d0ac89b046f9c1
https://doi.org/10.1109/sies.2012.6356600
https://doi.org/10.1109/sies.2012.6356600
Towards Accurate Source-Level Annotation of Low-Level Properties Obtained from Optimized Binary Code
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9781461414261
This chapter presents an approach for back-annotating timing information determined from optimized binary code into the source code of the software. The annotated source code can be integrated into a SystemC-based simulation environment and allows a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3220634b57db229bbdff2cf1a4c67c29
https://doi.org/10.1007/978-1-4614-1427-8_11
https://doi.org/10.1007/978-1-4614-1427-8_11