Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Stefan J. Weber"'
Autor:
D. Tobben, G.Y. Lee, Roy C. Iggulden, Stefan J. Weber, Maria Ronay, Jeff Gambino, Zhijian Lu, R.F. Schnabel, Clevenger Leigh Anne H, Gregory Costrini, R. Ramachandran, X.J. Ning, R. G. Filippi, Chenting Lin, David M. Dobuzinsky
Publikováno v:
Microelectronic Engineering. 50:265-270
This paper presents an overview of issues associated with Al dual damascene process technology. Different integration schemes are discussed and characteristics of metal fill, planarization and reliability are highlighted. Finally, a comparison is mad
Autor:
Stefan J. Weber, P Weigand, Roy C. Iggulden, R.F. Schnabel, S. B. Brodsky, Darryl D. Restaino, Lawrence A. Clevenger, E.A Mehter
Publikováno v:
Thin Solid Films. 320:63-66
Today, numerous different PVD techniques are used for the filling of sub micron contacts and vias in ULSI devices. One of the most promising approaches is the Al-reflow process. In this process, voids in vias which form during the PVD deposition of A
Autor:
R. C. Iggulden, G.Y. Lee, T. Matsunaga, X.J. Ning, H. Kitahara, Stefan J. Weber, T. Kirihata, E.W. Kiewra, B. Liegl, David L. Rath, G. Stojakovic, R. Ravikumar, R. G. Filippi
Publikováno v:
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).
Aluminum based wiring is common in the back-end-of-line (BEOL) metallization of DRAM chips. The 256 Mb DRAM chips necessitate the fabrication of wires at minimum pitch, especially when a stitched architecture is used. The critical topics related to e
Autor:
Stefan J. Weber, M. Hug, F. Zach, R. G. Filippi, K.P. Muller, J. Gambino, R.F. Schnabel, J.F. Nuetzel, Carl J. Radens, R. Iggulden, G. Mueller, Gary B. Bronner, Chenting Lin, David M. Dobuzinsky, Gregory Costrini, Larry Clevenger
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
A novel interconnect scheme is presented which has been used to significantly reduce the chip size of an 1 Gb SDRAM chip. The key element is the use of slotted vias for low resistance horizontal interconnects. This allows us to combine low capacitanc
Autor:
Stefan J. Weber, L. Yang, G.Z. Lu, R.F. Schnabel, D. Tobben, Chenting Lin, J. L. Hurd, Sunny Chiang, R. Filippi, J. Ning, Kenneth P. Rodbell, T. Gou, R. Longo, M. Ronay, Roderick C. Mosely, L. Gignac, Mark Hoinkis, R. Ploessl, S. Voss, Clevenger Leigh Anne H, Jeffrey P. Gambino, Lian-Yuh Chen, G. Costrini, D.M. Dobuzinsky, J.F. Nuetzel, R. C. Iggulden
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
As VLSI back end of line (BEOL) wiring is scaled to 0.175 /spl mu/m dimensions and sub-0.5 /spl mu/m pitches, the challenges to conventional Al RIE BEOL processes are the etching and the reliability of tall/narrow Al lines and the oxide gap fill and
Autor:
R. F. Schnabe, Stefan J. Weber, P. W. DeHaven, Kenneth P. Rodbell, Roy C. Iggulden, Clevenger Leigh Anne H
Publikováno v:
MRS Proceedings. 514
Interconnection metallization uses film stacks, often composed of thin ( and and Al reflections for a series of 20 nm Ti/ 10 nm TiN/400 nm AlCu films using both a conventional Siemens D500 diffractometer with a pole figure attachment and a Siemens HI