Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Stavros Simoglou"'
Publikováno v:
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::853d51163bcd798fe0942463e9400278
https://doi.org/10.1109/dft56152.2022.9962347
https://doi.org/10.1109/dft56152.2022.9962347
Publikováno v:
2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c48390c2f8a1e53e33c9f2c9b11397e8
https://doi.org/10.1109/vlsi-soc54400.2022.9939595
https://doi.org/10.1109/vlsi-soc54400.2022.9939595
Autor:
Christos Sotiriou, Nikolaos Sketopoulos, George Stamoulis, Dimitrios Garyfallou, Charalampos Antoniadis, Nestor Evmorfopoulos, Stavros Simoglou
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:962-972
As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a signifi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76064f51525fcb56921354f518082338
https://doi.org/10.1109/tvlsi.2021.3061484
https://doi.org/10.1109/tvlsi.2021.3061484
Publikováno v:
PATMOS
In this work, we present an Asynchronous Static Timing Analysis (ASTA) EDA methodology for cyclic, Asynchronous Control Circuits. Our methodology operates using Graph-based Analysis (GBA) principles, as conventional synchronous GBA STA, is fast, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::68aeb562068f76dbdf401ab88d5f0434
https://doi.org/10.1016/j.vlsi.2020.05.005
https://doi.org/10.1016/j.vlsi.2020.05.005
Publikováno v:
DFT
In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local sle
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a451e97ebbd491dbc0c663ae89c48955
https://doi.org/10.1109/dft52944.2021.9568296
https://doi.org/10.1109/dft52944.2021.9568296
Autor:
Milos Krstic, Marko Andjelkovic, Christos Sotiriou, Stavros Simoglou, I. Lilitsis, Christos Georgakidis
Publikováno v:
2021 IEEE 32nd International Conference on Microelectronics (MIEL).
The ever increasing demand for reliable microelectronic systems in the presence of radiation, combined with the continuous shrinking of CMOS technologies, has rendered the impact of radiation-induced voltage glitches, known as Single Event Transients
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f773065ba5eaeb97662efebdaf0cf0dd
https://doi.org/10.1109/miel52794.2021.9569180
https://doi.org/10.1109/miel52794.2021.9569180
Publikováno v:
ISVLSI
In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology uses Graph-based Analys
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::397ef6872626c581bab3755bb14f0d1d
https://doi.org/10.1109/isvlsi49217.2020.00078
https://doi.org/10.1109/isvlsi49217.2020.00078
Publikováno v:
ASYNC
In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d56cd82106cb6fdeed3903f6d60a84a4
https://doi.org/10.1109/async49171.2020.00008
https://doi.org/10.1109/async49171.2020.00008
Publikováno v:
DATE
Abax is a modern version of the classical Abacus, minimum displacement, greedy legaliser. Abax supports single-tier 2D or 3D legalisation for multiple, logic-on-logic 3D-IC tiers, efficient look-ahead legalisation of intermediate Global Placement (GP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6390735494521fabea03068382e3e44
https://doi.org/10.23919/date.2018.8342243
https://doi.org/10.23919/date.2018.8342243