Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Stanley M. Filipiak"'
Autor:
M. Jahanbani, Jon D. Cheek, N. Cave, S.j. Lian, Konstantin V. Loiko, Mehul D. Shroff, Chi-Hsi Wu, Stanley M. Filipiak, Xiang-Zheng Bo, H.C. Tuan, M. Azrak, Paul A. Grudowski, Wen-Jya Liang, Vance H. Adams, Sinan Goktepeli, Venkat R. Kolagunta, M. Foisy, John J. Hackenberg
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::33649abd039e0c65218d78c61cea5101
https://doi.org/10.1109/vlsit.2006.1705217
https://doi.org/10.1109/vlsit.2006.1705217
Autor:
Stanley M. Filipiak, Paul A. Grudowski, Brian J. Goolsby, Konstantin V. Loiko, M. Foisy, Venkat R. Kolagunta, D. Tekleab, Brian A. Winstead, Xiang-Zheng Bo, Sinan Goktepeli, Vance H. Adams
Publikováno v:
2006 International Conference on Simulation of Semiconductor Processes and Devices.
Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e856f411e2a7a44742f291e7e69bf5a
https://doi.org/10.1109/sispad.2006.282853
https://doi.org/10.1109/sispad.2006.282853
Autor:
Dan Babbitt, Cesar Garza, Stanley M. Filipiak, Patrick Montgomery, Richard Peters, Tab A. Stephens
Publikováno v:
SPIE Proceedings.
Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8048525f8c69c37ee8c6a641ec38e037
https://doi.org/10.1117/12.599918
https://doi.org/10.1117/12.599918
Autor:
L. Zhao, C. Esber, M. Aminpur, S. Park, Jeremy L. Martin, Stanley M. Filipiak, Cindy Kay Goldberg, T. Sparks, J. Mueller, J. Werking, Tab A. Stephens, E. Demircan, F. Huang
Publikováno v:
Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
This paper describes the integration of a silicon carbon nitride (SiCN) copper passivation and etch stop layer into a Cu low k dielectric interconnect technology. The incorporation of SiCN improves interconnect performance by virtue of its lower diel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01ebc3353e844d4b24d8599b53ad8137
https://doi.org/10.1109/iitc.2002.1014881
https://doi.org/10.1109/iitc.2002.1014881
Publikováno v:
Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
The use of low /spl kappa/ materials as the final intralayer dielectric (ILD) layer can impact the integrity of edge seals, blown fuses, and even the interface integrity at lower levels. Furthermore, the influence of the final ILD on lower levels dep
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc155396bea5310e194f4f7c3179fd14
https://doi.org/10.1109/iitc.2002.1014936
https://doi.org/10.1109/iitc.2002.1014936
Autor:
Seung-Chul Song, S. Venkatesan, A. Perera, Stanley M. Filipiak, Laegu Kang, F. Huang, Byoung W. Min, S. Tukunang, D. Menke, M. Turner, S.G.H. Anderson
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
Significantly reduced plasma damage is demonstrated by including a thin conductive top film (CTF) on the contact etch stop layer (ESL) for the first time, which effectively blocks radiation generated by subsequent high density plasma processes. We al
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c4fba2a5709c6f211b825bbfc766eaa
https://doi.org/10.1109/vlsit.2002.1015393
https://doi.org/10.1109/vlsit.2002.1015393
Autor:
C. Wang, J. Pellerin, A. Singhal, M. Aminpur, R. Chowdhury, Russell L. Carter, C. Prindle, T. Ryan, Kurt H. Junker, J. Iacoponi, Da Zhang, B. Melnick, L. Svedberg, N. Grove, E.J. Weitzman, M.-F. Ng, B. Brennan, J. Linville, T. Lii, Charles Fredrick King, Cindy Kay Goldberg, V. Wang, Jeremy L. Martin, P. Ventzek, J. Mueller, M. Kiene, J. Werking, M. Woo, S. Usmani, A. Guvenilir, Kirk J. Strozewski, Yuri E. Solomentsev, Kathleen C. Yu, Tab A. Stephens, Dean J. Denning, Stanley M. Filipiak, F. Huang, Janos Farkas, David Smith, Narayanan C. Ramani, P. Crabtree, T. Sparks, B. Wilson, John C. Flake, I. Shahvandi, Kevin E. Cooper, S. Kim, M. Olivares, B. Eggenstein
Publikováno v:
Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
The integration challenges of a low-k dielectric (k < 3) to form multi-level Cu interconnects for the next generation 0.1 /spl mu/m CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b62c9efc1f66fc1edd1c412d7acdaf8
https://doi.org/10.1109/iitc.2002.1014870
https://doi.org/10.1109/iitc.2002.1014870
Autor:
Kathleen A. Perry, Bich-Yen Nguyen, T. Saaranen, Matthew A. Thompson, Stanley M. Filipiak, L.B. La, Edward O. Travis, A.V. Gelatos, Navakanta Bhat, Phil Tobin, J. Peschke, R. Marsh
Publikováno v:
1995 Symposium on VLSI Technology. Digest of Technical Papers.
The report describes the integration of copper into the backend of a two-level metal 0.5 /spl mu/m BiCMOS SRAM circuit. The circuit is used to evaluate the impact of copper on the device characteristics. The results of time dependent gate dielectric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60ef79704298420c92400aa23570fa14
https://doi.org/10.1109/vlsit.1995.520842
https://doi.org/10.1109/vlsit.1995.520842
Autor:
K. Wehmer, K. Lee, Benjamin C. P. Ho, Jamie A. Vasquez, Stanley M. Filipiak, Kevin D. Lucas, B. Montgomery, Charles Fredrick King, C. Cook, David L. O'Meara, Anna Phillips
Publikováno v:
SPIE Proceedings.
As 248 nm DUV lithography is pushed to the 0.18 micrometers generation with logic features 0.14 micrometers and below, process control requirements become severe. Previously acceptable exposure latitude variations due to substrate reflectivity have b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52af88957f939a67898d8c0d66023821
https://doi.org/10.1117/12.350832
https://doi.org/10.1117/12.350832
Autor:
Dean J. Denning, Christopher C. Hobbs, Stanley M. Filipiak, P. Crabtree, S. Selinidis, Sam S. Garcia, R. Hershey, M. Olivares, T. Van Gompel, J. Defilippi, Nigel Cave, R. Mora, E.J. Weitzman, M. Lindell, J. Conner, K. H. Junker, G. Braekelmann, T. Newton, John J. Stankus, D. Jawarani, Katie Yu, David Smith, David Sieloff, Roc Blumenthal, K. Lee, J.J. Lee, T. Neil, T. Nguyen, C. Keyes, Melissa Freeman, Janos Farkas, J. T. Wetzel, R. Fox, M. Herrick, J. K. Watanabe, S. Kirksey, B. W. Fowler, T. Sparks, Jiming Zhang, D. Pena, R. Tiwari
Publikováno v:
MRS Proceedings. 564
The recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::daf0e2e7f893448b01d7137f7eca717a
https://doi.org/10.1557/proc-564-499
https://doi.org/10.1557/proc-564-499