Zobrazeno 1 - 10
of 32
pro vyhledávání: '"Stanley E. Schuster"'
Autor:
Richard E. Matick, Stanley E. Schuster
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:631-641
In this paper, a hierarchical differential sense amplifier for fast, low power DRAM arrays in logic-based eDRAM technology that operates with large parameter variations is described. Unique features of the hierarchical sense amplifier include its sho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a063f148e6fc8ea890552e94672ba69
https://doi.org/10.1109/jssc.2008.2010811
https://doi.org/10.1109/jssc.2008.2010811
Autor:
C. Tanner, K. Yanagisawa, Richard E. Matick, J. Griesemer, Hillery C. Hunter, Babar A. Khan, Paul C. Parries, Kim Hoki, John W. Golz, Subramanian S. Iyer, Gregory J. Fredeman, J. Harig, John E. Barth, R.P. Havreluk, T. Kirihata, Stanley E. Schuster, William Robert Reohr
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:86-95
As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3dc46e0324a6411f1637ffbc2350b8b3
https://doi.org/10.1109/jssc.2007.908006
https://doi.org/10.1109/jssc.2007.908006
Autor:
Stanley E. Schuster, Richard E. Matick
Publikováno v:
IBM Journal of Research and Development. 49:145-165
The IBM logic-based eDRAM (embedded DRAM) technology integrates a trench DRAM (dynamic random access memory) storage-cell technology into a logic-circuit technology, merging the two previously separate technologies. Since its introduction in the 1970
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb9ae8082bafd67c427d4e0bc4906d9d
https://doi.org/10.1147/rd.491.0145
https://doi.org/10.1147/rd.491.0145
Autor:
Grigorios Magklis, Alper Buyuktosunoglu, S.G. Dropsbo, Pradip Bose, Peter W. Cook, Volkan Kursun, Stanley E. Schuster, David H. Albonesi, Rajeev Balasubramonian, Eby G. Friedman, Michael L. Scott, Greg Semeraro, Michael C. Huang, Sandhya Dwarkadas
Publikováno v:
Computer. 36:49-58
By using adaptive processing to dynamically tune major microprocessor resources, developers can achieve greater energy efficiency with reasonable hardware and software overhead while avoiding undue performance loss. Adaptive processors require few ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30f88559c8cefd5876ad49b10d7436c8
https://doi.org/10.1109/mc.2003.1250883
https://doi.org/10.1109/mc.2003.1250883
Publikováno v:
IBM Journal of Research and Development. 44:70-82
An n-channel insulated-gate field-effect transistor technology established at IBM Research has served as the basis for further development leading to FET memory. Designs and characteristics of experimental devices of 500 and 1000 A gate insulator thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::909ea01b00c02e09537b2a8bfe503d48
https://doi.org/10.1147/rd.441.0070
https://doi.org/10.1147/rd.441.0070
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1073-1079
On-chip test circuitry that provides 8-b-deep emitter-coupled logic (ECL) level patterns to 12 input pads of a 512-kb CMOS ECL static RAM (SRAM) at cycle times as fast as 1.4 ns has been built in a 0.8- mu m CMOS technology with L/sub eff/=0.5 mu m.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02dff8c48a4087d9cb04805877540bde
https://doi.org/10.1109/4.142604
https://doi.org/10.1109/4.142604
Autor:
J.W. Allan, R.L. Franch, B.A. Chappell, S.P. Klepner, Stanley E. Schuster, Terry I. Chappell, Rajiv V. Joshi
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:1577-1585
The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a450108798794829f3c8819e3936cb54
https://doi.org/10.1109/4.98975
https://doi.org/10.1109/4.98975
Autor:
J. Griesemer, C. Tanner, William Robert Reohr, John W. Golz, J. Harig, Babar A. Khan, S. S. Iyer, Hyun-Chul Kim, T. Kirihata, Stanley E. Schuster, R.P. Havreluk, John E. Barth, Gregory J. Fredeman, Richard E. Matick, K. Yanagisawa, Paul C. Parries, Hillery C. Hunter
Publikováno v:
ISSCC
A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA). The macro was characterized via a test chip fabricated in a 65nm SOI deep-trench
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f885479054fd673652676cdef5d88eff
https://doi.org/10.1109/isscc.2007.373506
https://doi.org/10.1109/isscc.2007.373506
Autor:
Stanley E. Schuster
Publikováno v:
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57ce7aeb6346bd151657b113249500c4
https://doi.org/10.1109/isscc.1987.1157186
https://doi.org/10.1109/isscc.1987.1157186
Publikováno v:
IEEE International Solid-State Circuits Conference.
The authors describe an experimental 128k CMOS ECL-(emitter-coupled-logic)-compatible static RAM which has pipelined architecture and circuit techniques providing 6.5-ns first access and 5-ns cycle operation for fully random read/write. Using an all-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::829f6fc6e47d5c8ff38a6012bb9e64a8
https://doi.org/10.1109/isscc.1989.48220
https://doi.org/10.1109/isscc.1989.48220