Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Stacey Son"'
Autor:
Peter Sewell, Khilan Gudka, David Chisnall, Alexander Richardson, Robert N. M. Watson, Alexandre Joannou, Stacey Son, John Baldwin, Edward Napierala, Michael Roe, Robert M. Norton, Nathaniel Wesley Filardo, Alfredo Mazzinghi, Simon W. Moore, Jessica Clarke, Jonathan Woodruff, Sam Ainsworth, Brooks Davis, Brett F. Gutstein, Peter G. Neumann, Lucian Paul-Trifu, A. Theodore Markettos, Hongyan Xia, Timothy M. Jones
Publikováno v:
Proceedings of the 41st IEEE Symposium on Security and Privacy (SP)
2020 IEEE Symposium on Security and Privacy (SP)
IEEE Symposium on Security and Privacy
2020 IEEE Symposium on Security and Privacy (SP)
IEEE Symposium on Security and Privacy
Use-after-free violations of temporal memory safety continue to plague software systems, underpinning many high-impact exploits. The CHERI capability system shows great promise in achieving C and C++ language spatial memory safety, preventing out-of-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::aca2234b627b684664fc034652d5b50c
Autor:
Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, Graeme Barnes, David Chisnall, Jessica Clarke, Brooks Davis, Lee Eisen, Nathaniel Wesley Filardo, Richard Grisenthwaite, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alexander Richardson, Peter Rugg, Peter Sewell, Stacey Son, Hongyan Xia
This technical report describes CHERI ISAv8, the eighth version of the CHERI architecture being developed by SRI International and the University of Cambridge. This design captures ten years of research, development, experimentation, refinement, form
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f5b2e44e3ab9cca15f234ee537f453d
Autor:
Michael Roe, Simon W. Moore, Alexandre Joannou, Khilan Gudka, Peter G. Neumann, Jonathan Woodruff, Robert Norton, J. Edward Maste, Stacey Son, A. Theodore Markettos, Ben Laurie, Robert N. M. Watson, Brooks Davis, David Brazdil, David Chisnall
Publikováno v:
ASPLOS
Java provides security and robustness by building a high- level security model atop the foundation of memory protection. Unfortunately, any native code linked into a Java program – including the million lines used to implement the standard library
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::45826b388701e9ab0d83cd07e7650eab
https://doi.org/10.1145/3093315.3037725
https://doi.org/10.1145/3093315.3037725
Autor:
Robert N. M. Watson, Brooks Davis, Peter Sewell, Alexandre Joannou, Alfredo Mazzinghi, Nathaniel Wesley Filardo, Jonathan Woodruff, Alexander Richardson, Khilan Gudka, Jessica Clarke, Robert M. Norton, Ben Laurie, Stacey Son, David Chisnall, Simon W. Moore, Michael Roe, Peter G. Neumann, John Baldwin, Edward Napierala, J. Edward Maste, A. Theodore Markettos
Publikováno v:
ASPLOS
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
The CHERI architecture allows pointers to be implemented as capabilities (rather than integer virtual addresses) in a manner that is compatible with, and strengthens, the semantics of the C language. In addition to the spatial protections offered by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f1e757dbf0968dafc0479d4c9f8a8c46
Autor:
Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, Hongyan Xia
This technical report describes CHERI ISAv7, the seventh version of the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being developed by SRI International and the University of Cambridge. This design captur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5e58ff1ab5227b612ba7ee3a0b087fd
Autor:
Jonathan Anderson, Peter G. Neumann, Robert Norton, Stacey Son, Brooks Davis, Jonathan Woodruff, Alexandre Joannou, Nirav H. Dave, Khilan Gudka, Ed Maste, Steven J. Murdoch, A. Theodore Markettos, Michael Roe, Simon W. Moore, Colin Rothwell, Munraj Vadera, Ben Laurie, Robert N. M. Watson, David Chisnall
Publikováno v:
IEEE Micro. 36:38-49
Capability Hardware Enhanced RISC Instructions (CHERI) supplement the conventional memory management unit (MMU) with instruction-set architecture (ISA) extensions that implement a capability system model in the address space. CHERI can also underpin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2ae4b85c6e4842aeeda73fa15322bae7
https://doi.org/10.1109/mm.2016.84
https://doi.org/10.1109/mm.2016.84
Autor:
Peter G. Neumann, Stacey Son, Jonathan Woodruff, Alex Bradbury, Alfredo Mazzinghi, John Baldwin, David Chisnall, A. Theodore Markettos, Hongyan Xia, Robert N. M. Watson, Brooks Davis, Simon W. Moore, Alexander Richardson, Robert Kovacsics, Khilan Gudka, Michael Roe, Alexandre Joannou, Edward Napierala
Publikováno v:
ICCD
We characterize the cache behavior of an in-memory tag table and demonstrate that an optimized implementation can typically achieve a near-zero memory traffic overhead. Both industry and academia have repeatedly demonstrated tagged memory as a key me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7f0cdfed7d1944c80ac37005b3cab7b8
https://doi.org/10.1109/iccd.2017.112
https://doi.org/10.1109/iccd.2017.112
Autor:
Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Robert Norton, Stacey Son, Hongyan Xia
This technical report describes CHERI ISAv6, the sixth version of the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being developed by SRI International and the University of Cambridge. This design captures
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fef13cadfe1d4dde6901467851e260fb
Autor:
Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Jonathan Anderson, David Chisnall, Brooks Davis, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Robert Norton, Stacey Son, Hongyan Xia
This technical report describes CHERI ISAv5, the fifth version of the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being developed by SRI International and the University of Cambridge. This design captures
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f08e637d465632e01446cc6ade22c745
Autor:
Brooks Davis, Robert Norton, Stacey Son, David Chisnall, Khilan Gudka, Steven J. Murdoch, Robert N. M. Watson, Jonathan Anderson, Michael Roe, Peter G. Neumann, Nirav Dave, Simon W. Moore, Jonathan Woodruff, Ben Laurie, Munraj Vadera
Publikováno v:
IEEE Symposium on Security and Privacy
CHERI extends a conventional RISC Instruction-Set Architecture, compiler, and operating system to support fine-grained, capability-based memory protection to mitigate memory-related vulnerabilities in C-language TCBs. We describe how CHERI capabiliti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::774ce2159cde75b435727c8b2c7cd018
https://doi.org/10.1109/sp.2015.9
https://doi.org/10.1109/sp.2015.9