Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Srinivas T. Reddy"'
Autor:
Mark Bourgeault, David Galloway, Gregg William Baeckler, Elias Ahmed, Andy L. Lee, David Lewis, Boris Ratchev, Sandy Marquardt, Christopher F. Lane, Richard G. Cliff, Srinivas T. Reddy, Bruce B. Pedersen, Michael D. Hutton, Jay Schleicher, Paul Leventis, Giles Powell, Cameron McClintock, Kevin Stevens, David Cashman, Jonathan Rose, Ketan Padalia, Vaughn Betz, Richard Yuan
Publikováno v:
FPGA
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits cont
Autor:
Srinivas T. Reddy, David Lewis, Paul Leventis, Giles Powell, Richard G. Cliff, Christopher F. Lane, Chris Wysocki, Sandy Marquardt, Cameron McClintock, Andy L. Lee, David Jefferson, Bruce B. Pedersen, Jonathan Rose, Vaughn Betz
Publikováno v:
FPGA
This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing archit
Autor:
C. McClintock, John E. Turner, A. Lee, David Jefferson, Richard G. Cliff, R. Altaf, Bruce B. Pedersen, J. Schleicher, K. Zaveri, M. Mejia, Christopher F. Lane, Srinivas T. Reddy, Frank Heile, N. Ngo
Publikováno v:
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
Altera has developed a next generation architecture called APEX/sup TM/ to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system
Autor:
V. Singhal, A. Gupta, Kerry Veenstra, Joseph Huang, Craig Schilling Lytle, Ricky W. Ho, Srinivas T. Reddy, Frank Heile, S. Mashruwala, Rina Raman, C.K. Sung, Bruce B. Pedersen, L.T. Cope, Richard G. Cliff, Bahram Ahanin
Publikováno v:
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
A novel architecture called FLEX (flexible logic element matrix) has been designed which supports high logic densities up to 24,000 gates, maximizing overall system performance in a user design. This has been accomplished through a dual granularity a
Autor:
William Leong, C.K. Sung, Richard G. Cliff, David Jefferson, C. McClintock, Srinivas T. Reddy, Wanli Chang, John E. Turner, Joseph Huang, T. Cope, Christopher F. Lane, Bahram Ahanin, Bonnie I. Wang
Publikováno v:
Proceedings of Custom Integrated Circuits Conference.
An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs
Autor:
David Jefferson, Cameron McClintock, Ninh D. Ngo, Ketan Zaveri, Manuel Mijia, Richard G. Cliff, Christopher F. Lane, Srinivas T. Reddy, Wanli Chang
Publikováno v:
FPGA