Zobrazeno 1 - 10
of 75
pro vyhledávání: '"Srikanth Venkataraman"'
Autor:
Hari Addepalli, Irith Pomeranz, Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
Publikováno v:
2022 IEEE 31st Asian Test Symposium (ATS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f9a9f11dba7679bd12bf262d57dca738
https://doi.org/10.1109/ats56056.2022.00033
https://doi.org/10.1109/ats56056.2022.00033
Autor:
Edward Brazil, Janusz Rajski, Srikanth Venkataraman, Rudrajit Dutta, Anja Fast, Peter Maxwell, Will Howell, A. Glowatz, Friedrich Hapke
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40:584-597
This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::914235117db8d663555c539dcadb0c91
https://doi.org/10.1109/tcad.2020.3001259
https://doi.org/10.1109/tcad.2020.3001259
Autor:
Srikanth Venkataraman, Irith Pomeranz
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:5261-5266
Fail data is collected on a tester to allow defect diagnosis to be carried out. The high volume of fail data that some faulty units produce, and the test application time, motivated the development of procedures for terminating the fail data collecti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bda1408dd5a51c8413f3960e7842d02f
https://doi.org/10.1109/tcad.2020.2971527
https://doi.org/10.1109/tcad.2020.2971527
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 24:1-19
Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Lay
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8265fcc055d5ea7d34007866f26fcac1
https://doi.org/10.1145/3325066
https://doi.org/10.1145/3325066
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 22:1-17
As part of a yield improvement process, fail data is collected from faulty units. Several approaches exist for reducing the tester time and the volume of fail data that needs to be collected based on the observation that a subset of the fail data is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::795fece8ba171f92f0f516876f536039
https://doi.org/10.1145/3065925
https://doi.org/10.1145/3065925
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1497-1505
During fail data collection, a tester collects information that is useful for defect diagnosis. If fail data collection can be terminated early, the tester time as well as the volume of fail data will be reduced. Test reordering can enhance the abili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::234ad41a47aa5b9be7fb79a886a6097c
https://doi.org/10.1109/tvlsi.2016.2628321
https://doi.org/10.1109/tvlsi.2016.2628321
Publikováno v:
VTS
Multiple defects are prevalent in early stages of yield improvement for a new technology. When a logic diagnosis procedure is applied to a faulty unit that contains a multiple defect, it sometimes produces a large set of candidate faults. Such a set
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed6eae97f0ea6b0af54e5108fc6e12ba
https://doi.org/10.1109/vts.2019.8758663
https://doi.org/10.1109/vts.2019.8758663
Publikováno v:
DATE
As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2eb85868e228144dfa8013dff20afcf3
https://doi.org/10.23919/date.2019.8715037
https://doi.org/10.23919/date.2019.8715037
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:1198-1202
With the increasing transistor count and design complexity of modern integrated circuits, a large volume of fail data is collected by the tester for a failing die. This fail data is analyzed by a diagnosis procedure to obtain information about the de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bab7ec0141f19626a957eb6ac2e25389
https://doi.org/10.1109/tvlsi.2015.2432717
https://doi.org/10.1109/tvlsi.2015.2432717
Autor:
Srikanth Venkataraman, W. Redemund, Janusz Rajski, Rudrajit Datta, A. Glowatz, J. Schmerberg, Friedrich Hapke, W. Howell, A. Fast, E. Brazil
Publikováno v:
ITC
This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6eee1ac50a9b1f8835526e2f751295a1
https://doi.org/10.1109/test.2018.8624906
https://doi.org/10.1109/test.2018.8624906