Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Srikanth Arekapudi"'
Autor:
Russell Schreiber, Guhan Krishnan, Dave Johnson, Hugh McIntyre, Jim Farrell, David Akeson, Samuel D. Naffziger, Srikanth Arekapudi, Jonathan White, Benjamin Munger, Tom Burd, Kathryn Wilcox, Edward J. McLellan, Harry R. Fair, Sriram Sundaram
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:105-116
AMD's 6th generation “Carrizo” APU, targeted at 12–35 W mobile computing form factors, contains 3.1 billion transistors, occupies 250.04 mm $^{2}$ and is implemented in a 28 nm HKMG planar dual-oxide FET technology with 12 metal layers. The des
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a089cf76bdaf00a057a814330c1542d
https://doi.org/10.1109/jssc.2015.2464688
https://doi.org/10.1109/jssc.2015.2464688
Autor:
A. Ishii, Marios C. Papaefthymiou, Charles Ouyang, Visvesh S. Sathe, Srikanth Arekapudi, Samuel D. Naffziger
Publikováno v:
ISSCC
AMD's 4+ GHz x86–64 core codenamed “Piledriver” employs resonant clocking [1–4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1884f195f606eb2ccde8150b4e58b1be
https://doi.org/10.1109/jssc.2012.2218068
https://doi.org/10.1109/jssc.2012.2218068
Autor:
Tim Fischer, T. Meneghini, Samuel D. Naffziger, Hugh McIntyre, Eric W. Busta, James Vinh, Srikanth Arekapudi, Golden Michael L, Aaron Horiuchi
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:164-176
This paper describes key circuit innovations in a new x86-64 micro-architecture AMD code-named “Bulldozer” , . It is implemented in 32 nm high-K metal gate SOI CMOS. It occupies 30.9 mm-2, contains 213 million transistors, reduces the number of F
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::312e208e7fd70a06a729e2fc2dd79b12
https://doi.org/10.1109/jssc.2011.2167823
https://doi.org/10.1109/jssc.2011.2167823
Publikováno v:
IEEE Micro. 25:70-78
Efficient router architectures should have predictable throughput and scalable capacity, as well as internal optical technology (such as optical switches and wavelength division multiplexing) that can increase capacity by reducing power consumption.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::efa4aa8f3b5da2f5684ffe802bb4b9d8
https://doi.org/10.1109/mm.2005.23
https://doi.org/10.1109/mm.2005.23
Publikováno v:
Journal of Circuits, Systems and Computers. 12:305-332
Globally Asynchronous, Locally Synchronous (GALS) systems are now commonplace in many cost-critical and life-critical applications, thus motivating the need for a systematic approach to verify functionality. The complexity of the verification problem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64bf68d8fa0ec165ed9b05c5a846f897
https://doi.org/10.1142/s0218126603000775
https://doi.org/10.1142/s0218126603000775
Autor:
Carl D. Dietz, Tim Fischer, James Vinh, Samuel D. Naffziger, Kevin A. Hurd, Kathryn Wilcox, Dave Johnson, Jonathan White, Scott A. Hilker, Aaron Horiuchi, Srikanth Arekapudi, Golden Michael L, Hugh McIntyre, Eric W. Busta
Publikováno v:
ISSCC
AMD's 2-core “Bulldozer” module contains 213 million transistors in an 11-metal layer 32nm HKMG SOI CMOS process and is designed to operate from 0.8 to 1.3V. This new micro-architecture [1] improves performance and frequency while reducing area a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f97e94f96e6f6b36734e9365acb7dddb
https://doi.org/10.1109/isscc.2011.5746227
https://doi.org/10.1109/isscc.2011.5746227
Autor:
Srikanth Arekapudi, K. McGrath, Lowell Herlinger, M. Haertel, Greg Dabney, M. Singh, V. Palisetti, Golden Michael L, S. Hale, Y. Kim
Publikováno v:
ISSCC
A microprocessor featuring 2 Hammer cores and an on-chip DDR2 memory controller implements Pacifica architectural support for virtualization. It is fabricated in a 90nm triple-Vt partially-depleted SOI process with 9 layers of copper interconnect. Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f13d559908e1044bc52c6fbd277c9e20
https://doi.org/10.1109/isscc.2006.1696063
https://doi.org/10.1109/isscc.2006.1696063
Publikováno v:
Hot Interconnects
The load-balanced switch architecture is a promising way to scale router capacity. We explained previously (Keslassy, I. et al., Proc. ACM SIGCOMM, 2003) how it can be used to build a 100 Tb/s router with no centralized scheduler, no memory operating
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81732ef718a919704d7ea18e80c8f9f0
https://doi.org/10.1109/conect.2004.1375201
https://doi.org/10.1109/conect.2004.1375201