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pro vyhledávání: '"Sriharsha Enjapuri"'
Publikováno v:
VLSI Design
The paper presents SRAM cache design in 5nm FinFET technology for L2/L3 cache applications, demonstrating circuit techniques to enable wide-range DVFS (Dynamic Voltage and Frequency scaling) operation. CPU L2/L3 SRAM cache must achieve higher density
Publikováno v:
2014 International Conference on Embedded Systems (ICES).
Mathematical applications such as DFT and convolution are two main and common operations in signal processing applications. Many other Signal processing algorithms such as filter, spectrum estimation and OFDM can be transformed into DFT to implement