Zobrazeno 1 - 10
of 28
pro vyhledávání: '"Srihari Makineni"'
Autor:
Mike Upton, Ravi Iyer, Xiaowei Jiang, Li Zhao, Donald Newell, Niti Madan, Rajeev Balasubramonian, Srihari Makineni, Yan Solihin
Publikováno v:
IEEE Micro. 31:99-108
Integrating large DRAM caches is a promising way to address the memory bandwidth wall issue in the many-core era. However, organizing and implementing a large DRAM cache imposes a trade-off between tag space overhead and memory bandwidth consumption.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb01cc666f961501e6ab9ed7b8a84e0f
https://doi.org/10.1109/mm.2010.100
https://doi.org/10.1109/mm.2010.100
Publikováno v:
IEEE Micro. 27:21-33
Building a large-scale CMP platform requires a deep investigation of core performance impact, cache hierarchy implications, and on- and off-die bandwidth requirements. simulation speed and flexibility constitute fundamental challenges in such an eval
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38d97581e57b443154ac91f7d4c44053
https://doi.org/10.1109/mm.2007.66
https://doi.org/10.1109/mm.2007.66
Publikováno v:
IEEE Transactions on Computers. 56:740-753
Data movement (memory copies) is a very common operation during network processing and application execution on servers. The performance of this operation is rather poor on today's microprocessors due to the following aspects: 1) Several long-latency
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f17de25739ae9537e28e7b651d8f8a2
https://doi.org/10.1109/tc.2007.1036
https://doi.org/10.1109/tc.2007.1036
Autor:
L. Cline, Donald Newell, I. Illikkal, David B. Minturn, Annie Foong, Ravi Iyer, Srihari Makineni, G. Regnier, Ram Huggahalli
Publikováno v:
Computer. 37:48-58
To meet the increasing networking needs of server workloads, servers are starting to offload packet processing to peripheral devices to achieve TCP/IP acceleration. Researchers at Intel Labs have experimented with alternative solutions that improve t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::301ee10565996483116f1b9f8f640470
https://doi.org/10.1109/mc.2004.223
https://doi.org/10.1109/mc.2004.223
Autor:
Andrew J. Herdrich, Ravishankar Iyer, Zhen Fang, Lin Li, Bin Li, Xiaowei Jiang, Li Zhao, Srihari Makineni
Publikováno v:
Euro-Par 2012 Parallel Processing ISBN: 9783642328190
Euro-Par
Euro-Par
Different virtual memory regions (e.g., stack and heap) have different properties and characteristics. For example, stack data are thread-private by definition while heap data can be shared between threads. Compared with heap memory, stack memory ten
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03e764c8a8fdff609e3a392656f92479
https://doi.org/10.1007/978-3-642-32820-6_24
https://doi.org/10.1007/978-3-642-32820-6_24
Autor:
Carlos Flores Fajardo, Bin Li, Li Zhao, German Fabila Garcia, Zhen Fang, Srihari Makineni, Xiaowei Jiang, Seung Eun Lee, Ravishankar R. Iyer, Steve R. King
Publikováno v:
ICS
High performance SoCs and CMPs integrate multiple cores and hardware accelerators such as network interface devices and speech recognition engines. Cores make use of SRAM organized as a cache. Accelerators make use of SRAM as special-purpose storage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3335c2073c7d45f9038221f94196f54
https://doi.org/10.1145/1995896.1995940
https://doi.org/10.1145/1995896.1995940
Autor:
Zhen Fang, Paul Brett, Srihari Makineni, Xiaowei Jiang, Li Zhao, Sadagopan Srinivasan, Chita R. Das, Asit K. Mishra, Ravishankar Iyer
Publikováno v:
HPCA
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primarily guided by the needs of single applications. However, as multiple appl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09c10ea57f73a606e2e1240b50108da4
https://doi.org/10.1109/hpca.2011.5749757
https://doi.org/10.1109/hpca.2011.5749757
Publikováno v:
Conf. Computing Frontiers
Chip-multiprocessor (CMP) architectures employ multi-level cache hierarchies with private L2 caches per core and a shared L3 cache like Intel's Nehalem processor and AMD's Barcelona processor. When designing a multi-level cache hierarchy, one of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bf15ce8ba5a3499a29981d71e611310
https://doi.org/10.1145/1787275.1787314
https://doi.org/10.1145/1787275.1787314
Autor:
Yan Solihin, Ravishankar Iyer, Donald Newell, Li Zhao, Rajeev Balasubramonian, Srihari Makineni, Niti Madan, Xiaowei Jiang, Mike Upton
Publikováno v:
HPCA
As manycore architectures enable a large number of cores on the die, a key challenge that emerges is the availability of memory bandwidth with conventional DRAM solutions. To address this challenge, integration of large DRAM caches that provide as mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff97364d97621c05169b694c87b97940
https://doi.org/10.1109/hpca.2010.5416642
https://doi.org/10.1109/hpca.2010.5416642
Publikováno v:
HiPC
Linden Lab's Second Life is the prominent Virtual World platform in the market today. Virtual Worlds like Second Life are emerging to be a main stream server workload because of their popularity due to richness of 3D content and immersive social expe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1118364aa9c7ee167467ce4ed484480a
https://doi.org/10.1109/hipc.2009.5433182
https://doi.org/10.1109/hipc.2009.5433182