Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Sribalan Santhanam"'
Autor:
Sribalan Santhanam
Publikováno v:
IEEE Solid-State Circuits Magazine. 12:81-82
Autor:
Zongjian Chen, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Dan Murray, Eric Shiu, Priya Ananthanarayanan, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tam, Pradeep Trivedi, James Wang, Ricky Wen, John Yong, Sukalpa Biswas, Brian Campbell, Hao Chen, Shailendra Desai, Shaishav Desai, Dominic Go, Rajat Goel
Publikováno v:
ISSCC
An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design tec
Autor:
L. O'Donnell, V. Sundaresan, Brian J. Campbell, Tuan Do, G. Yee, R. Blake, Donald A. Priore, N. Bunger, Daniel C. Murray, E. Supnet, D. Kidd, Ingino Joseph M, D. Rodriguez, M. Pearce, G. Yiu, Sribalan Santhanam, Jong Lee, M. Carlson, K. Anne, V. von Kaenel, J. Cheng, C. Vo, Robert Rogenmoser, S. Nishimoto, R. Wen, Dongwook Suh, Zongjian Chen, David A. Kruckemyer, M. Panich, Daniel W. Dobberpuhl, M. Oykher, R. Allmon
Publikováno v:
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major