Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Sreejith Kochupurackal Rajan"'
Autor:
Sreejith Kochupurackal Rajan, Bharath Ramakrishnan, Husam Alissa, Washington Kim, Christian Belady, Muhannad S Bakir
Publikováno v:
IEEE Access, Vol 10, Pp 59259-59269 (2022)
The stagnation of Dennard scaling along with the move towards heterogeneous 2.5D and 3D ICs is increasing the thermal design power (TDP) envelopes of general-purpose CPUs. With conventional cooling approaches such as air-cooling and cold plates, it i
Externí odkaz:
https://doaj.org/article/de8f10f5c0de4700aa5359b347744449
Publikováno v:
Embedded and Fan‐Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces. :261-287
Autor:
Ting Zheng, Muhannad S. Bakir, Sreejith Kochupurackal Rajan, Jonathan R. Brescia, Joe L. Gonzalez
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:2069-2076
This paper presents a novel die-level, rePlaceable INtegrated CHiplet (PINCH) assembly using a socketed platform. To enable the replaceability of this tightly-integrated system, the appropriate set of enabling technologies is required. To this end, t
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:2061-2068
This paper presents a novel substrate-agnostic self-alignment technology with submicron alignment accuracy targeted for heterogeneous integrated systems. This self-alignment technology, referred to as PSAS-to-PSAS self-alignment, incorporates positiv
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:1824-1834
Autor:
Muhannad S. Bakir, Joe L. Gonzalez, Gary S. May, Jessica D. Falcone, Maysam Ghovanloo, Ravi V. Bellamkonda, Pyungwoo Yeon, Sreejith Kochupurackal Rajan, Oliver Brand
Publikováno v:
IEEE Sensors Journal. 21:13837-13848
This paper presents a new micromachining (MEMS) fabrication, microassembly, and hermetic packaging process for free-floating neural probes ( $1.3\times1.3$ mm2 bath-tub shaped micromachined silicon die, which serves as a substrate that supports all p
Monolithic Microfluidic Cooling of a Heterogeneous 2.5-D FPGA With Low-Profile 3-D Printed Manifolds
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:974-982
Heterogeneous integration techniques such as 2.5-D system-in-packages (SiPs) present new challenges that include higher aggregate package power as well as increased thermal crosstalk between different chiplets due to their proximity. This creates the
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 10:1474-1481
A polylithic integration technology called heterogeneous interconnect stitching technology (HIST) is explored in this article. HIST provides both 2.5-D and 3-D integration capabilities enabled by multi-height and fine-pitch compressible microintercon
Publikováno v:
2021 IEEE International 3D Systems Integration Conference (3DIC).
Autor:
Aravind Dasu, Thomas E. Sarvey, Sreejith Kochupurackal Rajan, Gutala Ravi Prakash, Ankit Kaul, Muhannad S. Bakir
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 9:2393-2403
The 2.5-D integration is becoming a common method of tightly integrating heterogeneous dice with dense interconnects for efficient, high-bandwidth inter-die communication. While this tight integration improves performance, it also increases the chall