Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Sreehari Veeramachanen"'
Autor:
Aditya Anirudh Jonnalagadda, Uppugunduru Anil Kumar, Rishi Thotli, Satvik Sardesai, Sreehari Veeramachaneni, Syed Ershad Ahmed
Publikováno v:
IEEE Access, Vol 12, Pp 31036-31046 (2024)
The posit number system aims to be a drop-in replacement of the existing IEEE floating-point standard. Its properties- tapered precision and high dynamic range, allow a smaller size posit to almost match the performance of a much larger size floating
Externí odkaz:
https://doaj.org/article/9a41624ee347477cbe58f08bb6501d3e
Autor:
Sai Srinivas Chandra, R. Jagadeesh Kannan, B. Saravana Balaji, Sreehari Veeramachaneni, Sk. Noor Mahammad
Publikováno v:
Scientific Reports, Vol 13, Iss 1, Pp 1-34 (2023)
Abstract Untrusted third parties and untrustworthy foundries highlighted the significance of hardware security in the present-day world. Because of the globalization of integrated circuit (IC) design flow in the semiconductor industry, hardware secur
Externí odkaz:
https://doaj.org/article/cab6de60535c47d5ad6d0a825c349283
Autor:
Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S
Publikováno v:
IET Computers & Digital Techniques, Vol 15, Iss 1, Pp 12-19 (2021)
Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed u
Externí odkaz:
https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd
Publikováno v:
VLSI Design
In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched to