Zobrazeno 1 - 10
of 69
pro vyhledávání: '"Spyridon Vlassis"'
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 4, Pp 203-217 (2023)
In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is applied for the optimized design of an 8-bit dual-loop CDR, design
Externí odkaz:
https://doaj.org/article/77a432cef9bd4054a04e0376f380a6ec
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 13, Iss 2, p 32 (2023)
In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time
Externí odkaz:
https://doaj.org/article/de0fdc5259fb4cab82bb0b4c6bd57517
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 13, Iss 2, p 27 (2023)
This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltag
Externí odkaz:
https://doaj.org/article/56ad588498b74f689a12741273e5dde2
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 12, Iss 1, p 3 (2022)
This paper presents a novel circuit of a z−1 operation which is suitable, as a basic building block, for time-domain topologies and signal processing. The proposed circuit employs a time register circuit which is based on the capacitor discharging
Externí odkaz:
https://doaj.org/article/40d698e8a2c443e6827e31bd3fcf7d85
Publikováno v:
2022 Panhellenic Conference on Electronics & Telecommunications (PACET).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ae1efe676ffba7299c577b79caadd71
https://doi.org/10.1109/pacet56979.2022.9976372
https://doi.org/10.1109/pacet56979.2022.9976372
Publikováno v:
Journal of Low Power Electronics and Applications; Volume 13; Issue 2; Pages: 27
This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2ad4e673d59cf4b70e5a568093aa97cf
https://doi.org/10.1109/pacet56979.2022.9976361
https://doi.org/10.1109/pacet56979.2022.9976361
Publikováno v:
2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b945d3ab9e0da34961e464531477058e
https://doi.org/10.1109/icecs202256217.2022.9971106
https://doi.org/10.1109/icecs202256217.2022.9971106
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 9:379-389
A programmable continuous-time linear equalizer (CTLE) for multi-rate high speed serial interfaces (HSSI) is proposed in this paper. Our solution is compliant with the multi-data rates of 1.45, 2.9, 5.8 and 11.6 Gbps specified by the M-PHY rev.4 HSSI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ffd8f7a78204b9ca6d9f8c2a2ee63cd
https://doi.org/10.1109/tetc.2019.2893735
https://doi.org/10.1109/tetc.2019.2893735
Publikováno v:
MOCAST
This paper presents a novel time register circuit suitable for time-based or time-domain signal processing. The proposed circuit is based on the capacitor discharging method and is compensated against technology process and chip temperature variation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3231209394b5e3105d477c071fee58c
https://doi.org/10.1109/mocast52088.2021.9493414
https://doi.org/10.1109/mocast52088.2021.9493414
Publikováno v:
Circuits, Systems, and Signal Processing. 38:5883-5895
In this work, a novel differential active voltage attenuator that is capable of operating under low supply voltage and power consumption is presented. The proposed attenuator is based on bulk-driven MOS devices. Thanks to the use of the fully balance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::965dca3ee9235dc17a11fae91767cc42
https://doi.org/10.1007/s00034-019-01146-6
https://doi.org/10.1007/s00034-019-01146-6