Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Sotirios Athanasiou"'
Autor:
Asimina Dimara, Christos Sougles, Sotirios Athanasiou, Konstantinos Grigoropoulos, Panagiota Sfakianou, Alexios Papaioannou, Stelios Krinidis, Dimitrios Triantafyllidis, Ioannis Tzitzios, Christos-Nikolaos Anagnostopoulos, Aristoklis Karamanidis, Vaia Saltagianni, Dimosthenis Ioannidis, Dimitrios Tzovaras
Publikováno v:
Electrical Engineering.
Autonomous PV systems offer a substitute for or a safety net against the transmission and distribution companies’ rising and expanding electricity delivery fees. Across the world, delivery fees have climbed by about 3% annually while the cost of en
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2017, 180, pp.1-4. ⟨10.1016/j.mee.2017.05.008⟩
Microelectronic Engineering, Elsevier, 2017, 180, pp.1-4. ⟨10.1016/j.mee.2017.05.008⟩
International audience; Four-gate (G4-FET) transistors with ultrathin body and buried oxide (UTBB) are investigated. The devices were fabricated, measured and simulated in UTBB FD-SOI technology for the first time. The G4-FETs had either typical H-ga
Publikováno v:
IEEE Electron Device Letters
IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2017, 38 (2), pp.157-159. ⟨10.1109/LED.2016.2637563⟩
IEEE Electron Device Letters, 2017, 38 (2), pp.157-159. ⟨10.1109/LED.2016.2637563⟩
IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2017, 38 (2), pp.157-159. ⟨10.1109/LED.2016.2637563⟩
IEEE Electron Device Letters, 2017, 38 (2), pp.157-159. ⟨10.1109/LED.2016.2637563⟩
International audience; The supercoupling effect is demonstrated experimentally by monitoring the electron and hole currents in a field-effect transistor provided with p+ and n+ contacts. According to the polarity of the voltage applied to the front
Autor:
C. Vizioz, J.M. Hartmann, Maud Vinet, Sotirios Athanasiou, Jean-Charles Barbe, Francois Andrieu, Sebastien Martinie, Thomas Ernst, Olivier Rozeau, C. Comboroure, V. Lapras, Marie-Anne Jaud, François Triozon, Bernard Previtali, Joris Lacord, M.-P. Samson, Sylvain Barraud
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM)
2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. ⟨10.1109/IEDM.2017.8268473⟩
2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. ⟨10.1109/IEDM.2017.8268473⟩
International audience; This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobilit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5b9190e6358484ba7d58285a1e487aa1
https://hal-cea.archives-ouvertes.fr/cea-01973409/document
https://hal-cea.archives-ouvertes.fr/cea-01973409/document
Publikováno v:
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2017, 64 (3), pp.916-922. ⟨10.1109/TED.2017.2651363⟩
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2017, 64 (3), pp.916-922. ⟨10.1109/TED.2017.2651363⟩
Ultrathin bipolar + MOS (BiMOS) transistors were fabricated with 28-nm Ultra Thin Body and Buried oxide (UTBB) FD-SOI high-k metal gate technology for the first time. We evaluate the device behavior through dc/transmission line pulse measurements and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7ed34a30735496d67d7ed9ca5a62cb2d
https://hal.archives-ouvertes.fr/hal-02006376
https://hal.archives-ouvertes.fr/hal-02006376
Autor:
Sotirios Athanasiou, Ph. Galy
Publikováno v:
ICICDT
The purpose of this paper is to introduce preliminary results on thin silicon film TFET (gated diode) topology in 28 nm FD-SOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models and on si
Publikováno v:
2016 EUROSOI-ULIS Proceedings
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Jan 2016, Vienna, Austria. pp.151-154, ⟨10.1109/ULIS.2016.7440075⟩
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Jan 2016, Vienna, Austria. pp.151-154, ⟨10.1109/ULIS.2016.7440075⟩
session 11: Advanced Devices; International audience; We propose a novel device (GDNMOS: Gated Diode merged NMOS) fabricated with 28nm UTBB FD-SOI high-k metal gate technology. Variable electrostatic doping (gate-induced) in diode and transistor body
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6c47381e014c04a7ee3372b53b32c52e
https://hal.archives-ouvertes.fr/hal-02006258
https://hal.archives-ouvertes.fr/hal-02006258
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2016, 115, pp.192-200. ⟨10.1016/j.sse.2015.09.001⟩
Solid-State Electronics, Elsevier, 2016, 115, pp.192-200. ⟨10.1016/j.sse.2015.09.001⟩
International audience; We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ebec780ccc225ddf470342b3557291c3
https://hal.archives-ouvertes.fr/hal-02003184
https://hal.archives-ouvertes.fr/hal-02003184
Publikováno v:
2015 CAS Proceedings
2015 International Semiconductor Conference (CAS)
2015 International Semiconductor Conference (CAS), Oct 2015, Sinaia, Romania. pp.157-160, ⟨10.1109/SMICND.2015.7355193⟩
2015 International Semiconductor Conference (CAS)
2015 International Semiconductor Conference (CAS), Oct 2015, Sinaia, Romania. pp.157-160, ⟨10.1109/SMICND.2015.7355193⟩
International audience; In this paper, we introduce a new BIMOS transistor fabricated with 28nm high-k metal-gate FDSOI UTBB technology. The device is highly flexible and reconfigurable as it can be operated in MOS, Bipolar, Hybrid and 4-Gate modes.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::80cddb2e85be59e4e2f36eb66423be15
https://hal.archives-ouvertes.fr/hal-02004292
https://hal.archives-ouvertes.fr/hal-02004292
Publikováno v:
2015 S3S Proceedings
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2015, Rohnert Park, United States. pp.10a.3, ⟨10.1109/S3S.2015.7333482⟩
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2015, Rohnert Park, United States. pp.10a.3, ⟨10.1109/S3S.2015.7333482⟩
session: Power Management; International audience; We investigate the impact of carrier mobility on the performance of a novel Bipolar MOS (BiMOS) device fabricated in Ultra-Thin Body & BOX (UTBB) FDSOI technology. BiMOS transistor combines bipolar a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::16ae53c1e5f6c8191f5a9da3022876a2
https://hal.archives-ouvertes.fr/hal-02004284
https://hal.archives-ouvertes.fr/hal-02004284