Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Sophie Verrun"'
Autor:
Mathilde Gottardi, Gilles Romero, Pierre-Emile Philip, Céline Doussot, Sophie Verrun, Thierry Mourier, Gaelle Guittet, Vincent Mevellec
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2019:000077-000103
TSV integration is a key technology allowing heterogeneous devices 3D integration. However, depending on the targeted application, various TSV sizes and integration schemes exist, all requesting very high aspect ratio. The most common integration is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f4a2006946e837960775a3ef79c7448
https://doi.org/10.4071/2380-4491-2019-dpc-presentation_ta1_061
https://doi.org/10.4071/2380-4491-2019-dpc-presentation_ta1_061
Autor:
Jean Charbonnier, Pierre Tissier, R. Coquand, Gabriel Pares, Thierry Mourier, Sophie Verrun, R. Franiatte, Stephane Minoret, F. Allain, Mehmet Bicer, Myriam Assous, C. Ribiere
Publikováno v:
69th Electronic Components and Technology Conference
69th Electronic Components and Technology Conference, May 2019, Las Vegas, United States. pp.1622-1628, ⟨10.1109/ECTC.2019.00249⟩
69th Electronic Components and Technology Conference, May 2019, Las Vegas, United States. pp.1622-1628, ⟨10.1109/ECTC.2019.00249⟩
International audience; Micro pillars and micro bumps interconnections are considered as mature technology for 3-D integration and chip stacking. However, in the framework of high-energy particles detection as ATLAS Large Hadron Collider new tracker
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::112192c5ae8aee2a47a8c2ab0b5895a9
https://hal.archives-ouvertes.fr/hal-02475226
https://hal.archives-ouvertes.fr/hal-02475226
Autor:
Frédéric Ritton, Guillaume Rodriguez, Agathe André, Loubna El Melhaoui, Lilian Masarotto, Stephane Minoret, Pascale Parrein, Sophie Verrun, Laurent Frey
Publikováno v:
Optics Letters
Optics Letters, Optical Society of America-OSA Publishing, 2018, 43 (6), pp.1355. ⟨10.1364/OL.43.001355⟩
Optics Letters, 2018, 43 (6), pp.1355. ⟨10.1364/OL.43.001355⟩
Optics Letters, Optical Society of America-OSA Publishing, 2018, 43 (6), pp.1355. ⟨10.1364/OL.43.001355⟩
Optics Letters, 2018, 43 (6), pp.1355. ⟨10.1364/OL.43.001355⟩
International audience; New architectures of interference silver-dielectric multilayer filters inspired from induced transmission designs are investigated with the prospect of high-performance red-greenblue (RGB) complementary metal oxide semiconduct
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5e4d993e09ee6e8ee433f14ea7c3f621
https://doi.org/10.1364/ol.43.001355
https://doi.org/10.1364/ol.43.001355
Autor:
Laurent Ulmer, Jean-Pierre Blanc, Emmanuel Defay, Bernard Andre, Emmanuelle Serret, Sophie Verrun, Philippe Delpech, Marc Aid, Pierre Garrec, Julie Guillan, Denis Pellissier, Pascal Ancey, David Wolozan
Publikováno v:
Solid-State Electronics. 51:1624-1628
This paper describes realization and characterization of SrTiO 3 (STO) high K MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are connected to IC and are used as coupling capacitors in order to realize a high pass filter. Surf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3cfe2cfb16c8c58c781527689b149dad
https://doi.org/10.1016/j.sse.2007.09.036
https://doi.org/10.1016/j.sse.2007.09.036
Autor:
Francis Calmon, Alexis Farcy, A. Berthelot, Thierry Lacrevaz, Ian O'Connor, N. Chevrier, P. Coudrain, Sophie Verrun, O. Le-Briz, N. Bouzaida, Bernard Flechet, Jean Charbonnier, G. Cibrario, D. Henry, L. Fourneaud, R. Franiatte
Publikováno v:
IEEE 63rd Electronic Components and Technology Conf.
IEEE 63rd Electronic Components and Technology Conf., May 2013, Las Vegas, United States. pp.674-682
IEEE 63rd Electronic Components and Technology Conf., May 2013, Las Vegas, United States. pp.674-682
This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7d25cfe5fd1730fdf4cd764f23033d6f
https://hal.archives-ouvertes.fr/hal-01018405
https://hal.archives-ouvertes.fr/hal-01018405
Autor:
Sophie Verrun, Remy Franiatte, Vincent Mandrillon, Antoine Nowodzinski, Romain Anciant, Herve Boutry, Gilles Simon
Publikováno v:
2012 International Semiconductor Conference Dresden-Grenoble (ISCDG).
Micro-insert technology is a wafer level stacking technology offering main advantages such as simplicity, low cost and compatibility with chip assembly technologies. This paper presents recent preliminary reliability tests results. Thermal cycling te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67de20174e4b6d8e85725e3a891be150
https://doi.org/10.1109/iscdg.2012.6359983
https://doi.org/10.1109/iscdg.2012.6359983
Autor:
Jean Charbonnier, N. Sillon, Sophie Verrun, E. Saugier, M. Neyret, David Henry, L. Bonnot, Severine Cheramy, C. Brunet-Manquat, G. Garnier, Alexis Farcy, Maxime Rousseau, P. Chausse, Lionel Cadix
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
Today, a new trend in wafer level packaging is to add more than one die in the same package and, sometimes, to use the third dimension in order to : • Decrease the form factor of the final system • Improve the thermal and electrical performances
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::803bc0ea31ca2bebe227eba02b716fc8
https://doi.org/10.1109/eptc.2009.5416490
https://doi.org/10.1109/eptc.2009.5416490
Autor:
Patrick Leduc, Sophie Verrun, Laurent Bally, Marc Zussy, David Bouchu, Thomas Signamarcheix, Maxime Rousseau, Alexis Farcy, Lea Di Cioccio, Antonio Roman, Lionel Cadix, Nicolas Sillon, Myriam Assous
Publikováno v:
3DIC
Copper-filled Through-Si Vias (TSV) with diameters from 2 µm to 5 µm have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinnin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38e849ed707b283e9445a6688227f155
https://doi.org/10.1109/3dic.2009.5306602
https://doi.org/10.1109/3dic.2009.5306602
Autor:
M. Neyret, D. Henry, Sophie Verrun, E. Saugier, X. Gagnard, J. Charbonnier, N. Sillon, S. Cheramy, L. Bonnot, C. Brunet-Manquat, P. Chausse
Publikováno v:
3DIC
In this paper, the technological bricks specifically developed for 3D integration of a set top box demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1].
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::696ea27387bf9e82b71c8df425afa0e0
https://doi.org/10.1109/3dic.2009.5306561
https://doi.org/10.1109/3dic.2009.5306561
Autor:
Laurent Clavelier, Lea Di Cioccio, Myriam Assous, Jerome Dechamp, Thomas Signamarcheix, Patrick Leduc, Rachid Taibi, Laurent Vandroux, Laurent Bally, Marc Zussy, Sophie Verrun, Francois de Crecy, Laurent-Luc Chapelon, D. Bouchu, Pierric Gueguen
Publikováno v:
3DIC
An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::075f74f34c4fa4f5367c59879f00ad36
https://doi.org/10.1109/3dic.2009.5306534
https://doi.org/10.1109/3dic.2009.5306534