Zobrazeno 1 - 10
of 95
pro vyhledávání: '"Sonja Sioncke"'
Autor:
Sonja Sioncke, Simone Gerardin, Ronald D. Schrimpf, Nadine Collaert, Bernardette Kunert, Simeng E. Zhao, Stefano Bonaldo, Jerome Mitard, Niamh Waldron, En Xia Zhang, Pan Wang, Daniel M. Fleetwood, Dimitri Linten, Alessandro Paccagnella, Rong Jiang, Robert A. Reed, Huiqi Gong
Publikováno v:
IEEE Transactions on Nuclear Science. 66:1599-1605
We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at $V_{\mathrm {G}} = -1$ V. Radiation-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c14d19995dea10c70b86f978654d6a44
https://doi.org/10.1109/tns.2019.2890827
https://doi.org/10.1109/tns.2019.2890827
Beyond SiliconMOS : An Electrical Study on Interface and Gate Dielectrics withac Admittance Techniques
Autor:
Abhinav Gaur, Guy Brammertz, Laura Nyns, Sonja Sioncke, A. Vais, Iuliana Radu, Nadine Collaert, Alireza Alian, Dennis Lin, Inge Asselberghs, Annelies Delabie, Marc Heyns, Kristin De Meyer
Publikováno v:
Materials Science and Technology
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7cd7b60bb9f1a12c0d6635f07a8b3b4d
https://doi.org/10.1002/9783527603978.mst0480
https://doi.org/10.1002/9783527603978.mst0480
Autor:
Marc Heyns, Aaron Thean, Dan Mocuta, Laura Nyns, V. Putcha, Xiang Jiang, Jacopo Franco, Nadine Collaert, Arturo Sibaja Hernandez, Valentina Spampinato, Alexis Franquet, Dimitri Linten, Jerome Mitard, Sonja Sioncke, Fu Tang, Jan Willem Maes, Michael Eugene Givens, Qi Xie, Rita Rooyackers, A. Vais, Sergio Calderon Ardila
Publikováno v:
Advances in Science, Technology and Engineering Systems, Vol 3, Iss 5, Pp 36-44 (2018)
In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiOx layer in the gate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2f90282291f65b09e4873a69c32b11c9
https://astesj.com/v03/i05/p06/
https://astesj.com/v03/i05/p06/
Autor:
Rong Jiang, Dimitri Linten, Nadine Collaert, En Xia Zhang, Wenjun Liao, Chundong Liang, Sonja Sioncke, Ronald D. Schrimpf, Niamh Waldron, Jerome Mitard, Robert A. Reed, Daniel M. Fleetwood, Simeng E. Zhao
Publikováno v:
IEEE Transactions on Nuclear Science. 65:175-183
We use capacitance–frequency ( $C$ – $f$ ) measurements to provide lower bound estimates of border-trap densities in multifin MOS capacitors with high-K dielectrics built in Ge and InGaAs fin field effect transistor (FinFET) technologies before a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52cf205f64e15acd9fddde62955d50bd
https://doi.org/10.1109/tns.2017.2761298
https://doi.org/10.1109/tns.2017.2761298
Autor:
Dennis Lin, Sonja Sioncke, Xiaoqiang Jiang, V. Putcha, Nadine Collaert, Kristin De Meyer, Aaron Thean, Fu Tang, Laura Nyns, Michael Eugene Givens, A. Vais, Jacopo Franco, Qi Xie, Anda Mocuta, Jan Willem Maes, Koen Martens
Publikováno v:
IEEE Electron Device Letters. 38:318-321
This letter proposes a metric to assess the quality of high-k dielectrics on III–V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, ${V}_{t}$ . The metric is b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a34f3f0f4d5898224719859f7489d1ac
https://doi.org/10.1109/led.2017.2657794
https://doi.org/10.1109/led.2017.2657794
Autor:
V. Putcha, D. Zhou, Hiroaki Arimura, Liesbeth Witters, Nadine Collaert, Sonja Sioncke, Niamh Waldron, Alireza Alian, D. Linten, Laura Nyns, Guido Groeseneken, A. Vais, M.M. Heyns, B. Kaczer, J. Franco, Aaron Thean, Jerome Mitard
Publikováno v:
MRS Advances. 1:3329-3340
We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::07e6a51548462accbe5acc43644bf44e
https://doi.org/10.1557/adv.2016.387
https://doi.org/10.1557/adv.2016.387
Publikováno v:
IRPS
Charge trapping in the gate-oxide can cause significant degradation and reduce the operating lifetime of the device. Here, we study the kinetics of charge trapping in the InGaAs/Al 2 O 3 /HfO 2 gate-stack using Capture and Emission Time (CET) maps. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e99a334bef62d4a6929fe5d51ecb550
https://doi.org/10.1109/irps.2018.8353603
https://doi.org/10.1109/irps.2018.8353603
Autor:
J. Franco, Niamh Waldron, Gerhard Rzepa, V. Putcha, Sonja Sioncke, M.M. Heyns, B. Kaczer, Nadine Collaert, Guido Groeseneken, A. Vais, Ph. J. Roussel, D. Linten, D. Zhou, Tibor Grasser
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7dd33132ba8647085c97de5c1d438637
https://doi.org/10.1109/iedm.2017.8268347
https://doi.org/10.1109/iedm.2017.8268347
Autor:
Sonja Sioncke, Daire J. Cott, Serena Iacovo, Aaron Thean, Valery V. Afanas'ev, Hiroaki Arimura, Andre Stesmans
Publikováno v:
Microelectronic Engineering. 147:180-183
Graphical abstractDisplay Omitted Charge traps in (100)Ge/Sc2O3/HfO2 stacks are studied by ESR and electrical probing.The utility of Sc2O3 as passivation layer on Ge is studied by conventional ESR.Trapping centers in (100)Ge/Sc2O3 entities are tracke
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f042b0131efb6aabe87393a8a8e7fc26
https://doi.org/10.1016/j.mee.2015.04.071
https://doi.org/10.1016/j.mee.2015.04.071
Autor:
Nadine Collaert, Eddy Simoen, Anda Mocuta, Cor Claeys, Sonja Sioncke, Hans Mertens, Hiroaki Arimura, Chao Zhao, Jun Luo, Wen Fang, Aaron Thean, Jerome Mitard
Publikováno v:
IEEE Transactions on Electron Devices. 62:2078-2083
The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeO x interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/ $f^{\gamma }$
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d46cb12fd7f596bfa989d6b3eff45675
https://doi.org/10.1109/ted.2015.2430367
https://doi.org/10.1109/ted.2015.2430367