Zobrazeno 1 - 8 of 8 pro vyhledávání: '"Sonarith Chhun"'
1
Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes
Autor: Sonarith Chhun, Laurent Vallier, Alain Campo, Gilles Cunge, Côme de Buttet, Philippe Garnier, S. Zoll, Emilie Prevost, Thomas Massin, Patrick Maury
Publikováno v: SPIE Proceedings.
Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etch
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::261ab2cd95fd4103d27f92bd846b003a
https://doi.org/10.1117/12.2257971
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2
New generation of reactive pre-clean prior to barrier–seed deposition to preserve ULK integrity
Autor: M. Delavant, Denis Guiheux, S. Guggilla, T. H. Ha, J. Guillan, D. Galpin, Marc Juhel, S. Hong, John C. Forster, P. Jian, Sonarith Chhun, B. Bozon
Publikováno v: Microelectronic Engineering. 92:38-41
Advanced interconnects development requires introduction of porous ultra low k (ULK) dielectrics enhancing product performance through parasitic capacitance reduction. ULK layers are characterized by higher carbon content and lower mechanical propert
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f8641d07ab4d3cfda43a4d8300a50527
https://doi.org/10.1016/j.mee.2011.05.038
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3
New generation of Self Ionized Plasma copper seed for sub 40nm nodes
Autor: M. C. Luche, J. Guillan, Sonarith Chhun, P. Normandon, E. Petitprez, Lucile Arnaud, K. Haxaire, E. Richard, C. Monget, D. Galpin
Publikováno v: Microelectronic Engineering. 88:697-700
Two seed deposition hardware are compared in this paper: a standard Self Ionized Plasma (SIP) standard chamber and a new generation chamber allowing Cu deposition and re-sputtering simultaneously. TEM characterizations exhibits better features covera
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::401122ea0f103eb2d28de83c4e50ef30
https://doi.org/10.1016/j.mee.2010.07.035
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4
32nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3
Autor: D. Galpin, Alexis Farcy, E. Richard, P. Brun, G. Imbert, Jonathan Pradelles, Vincent Jousseaume, M. Assous, B. Icard, Daniel Barbier, C. Jayet, C. Monget, Sonarith Chhun, Michel Haond, Sylvain Maitrejean, Vincent Arnal, J. Guillan, S. Manakli, K. Hamioud, Aziz Zenasni
Publikováno v: Microelectronic Engineering. 87:316-320
A 32nm node BEOL integration scheme is presented with 100nm metal pitch at local and intermediate levels and 50nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32nm RC performance specifications, extreme low-k (ELK) porous SiOCH k
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8e61fa6273f887f806348d3683ae5ac2
https://doi.org/10.1016/j.mee.2009.07.008
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5
Demonstration of TFHM scalability to 32 nm node BEOL interconnect and extendibility to ELK k ≤ 2.3 dielectric material
Autor: Sylvain Maitrejean, J. Guillan, Vincent Jousseaume, Jonathan Pradelles, D. Galpin, Aziz Zenasni, Michel Haond, Olivier Gourhant, S. Manakli, Sonarith Chhun, K. Hamioud, M. Vilmay, E. Richard, G. Imbert, P. Brun, C. Monget, D. Barbier, B. Icard, Alexis Farcy, Vincent Arnal, C. Jayet, M. Assous
Publikováno v: 2009 IEEE International Interconnect Technology Conference.
A 32 nm node BEOL demonstrator using Trench First Hard Mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::713e7a42b5208b35772e44a54a9caec1
https://doi.org/10.1109/iitc.2009.5090370
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6
Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact
Autor: Laurent-Georges Gosset, Sonarith Chhun, W Besling, Cedric Bermond, Thierry Lacrevaz, Vincent Arnal, F. de Crecy, O. Cueto, Alexis Farcy, G. Angenieux, O. Rousire, Joaquim Torres, B. Blampey, Bernard Flechet
Publikováno v: Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..
Due to the continuous shrink of technology dimensions, parasitic propagation delay time and crosstalk at interconnect levels increasingly affect overall circuit performances. New materials, processes and architectures are now required to improve BEOL
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::15088eba86e463335fa61a0f4c0b9f43
https://doi.org/10.1109/iitc.2005.1499929
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7
Investigation of an advanced SiH/sub 4/ based self-aligned barrier process for Cu BEOL reliability performance improvement on industrial 110 nm technology
Autor: Marc Juhel, P. Dumont-Girard, Sonarith Chhun, G. Bryce, Laurent-Georges Gosset, Joaquim Torres, C. Prindle, V. Girault
Publikováno v: Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..
The paper deals with the introduction of an innovative self-aligned capping layer leading to the formation of a Cu/Si/N mixed interface. The process was first developed targeting the aggressive 65 nm technology node and below. After optimisation, the
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ebf35f1e55d72a21669245402e37da26
https://doi.org/10.1109/iitc.2005.1499953
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