Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Somayeh Sadeghi-Kohan"'
Publikováno v:
Journal of Electronic Testing. 37:715-728
Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8e9977bbb1cc1af3d3bc0795f21c082a
https://doi.org/10.1007/s10836-021-05979-5
https://doi.org/10.1007/s10836-021-05979-5
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 8:627-641
Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1002114315024130dc7d75e7ce40e30b
https://doi.org/10.1109/tetc.2017.2771441
https://doi.org/10.1109/tetc.2017.2771441
Publikováno v:
DFT
In today’s system-on-chips, interconnects increasingly affect the reliability of the system. Crosstalk defects can result in delay and glitch faults and also aggravate aging mechanisms such as electro-migration. Furthermore, fab-induced deviations
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3fdd7282e3e008a681d66fe3dc0669b7
https://doi.org/10.1109/dft50435.2020.9250922
https://doi.org/10.1109/dft50435.2020.9250922
Publikováno v:
VTS
In today’s system-on-chips, interconnect has an important role and affects the system’s reliability more than in conventional technologies. Interconnects suffer from crosstalk defects that result in delay and glitch faults. Furthermore, fab-induc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a99d07e712a40217f99294b26f8c4d27
https://doi.org/10.1109/vts48691.2020.9107591
https://doi.org/10.1109/vts48691.2020.9107591
Publikováno v:
IOLTS
Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7c151e45279506bd4751b301c16e0ba
https://doi.org/10.1109/iolts.2018.8474120
https://doi.org/10.1109/iolts.2018.8474120
Publikováno v:
2016 IEEE East-West Design & Test Symposium (EWDTS)
EWDTS
EWDTS
In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simpl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::262232cfc9b11875a95d21b9997c43fc
Publikováno v:
DTIS
Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Sele
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbcc7b72d7c064e151e9c992578dafe5
https://doi.org/10.1109/dtis.2015.7127373
https://doi.org/10.1109/dtis.2015.7127373
Publikováno v:
DTIS
Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that col
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6fed0927d60c40a99d8ab25adab601af
https://doi.org/10.1109/dtis.2015.7127368
https://doi.org/10.1109/dtis.2015.7127368
Publikováno v:
ETS
This paper presents an off-line interconnect test methodology that implements the MDSI (Maximal Dominant Signal Integrity) crosstalk fault model. The test methodology consists of MDSI test pattern generators and response analyzers that are incorporat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6f59e30b5d2dce9a0bd71711f8402e7
https://doi.org/10.1109/ets.2014.6847847
https://doi.org/10.1109/ets.2014.6847847
Publikováno v:
ETS
In this paper, we introduce a formal and scalable debugging approach to derive a reduced ordered set of design error candidates in polynomial datapath designs. To make our debugging method scalable for large designs, we utilize a Modular Horner Expan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d884cbd642f02648dc1e79417566f24f
https://doi.org/10.1109/ets.2014.6847797
https://doi.org/10.1109/ets.2014.6847797