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pro vyhledávání: '"Soft IP"'
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Procedural generators are often proposed for analog IC design automation. They promise to encapsulate designer knowledge and intellectual property (IP) data in a deterministic and reusable way. While recent developments claim to have proven this, one
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a9a4c7834d747fad55f415d010674159
Publikováno v:
ISCAS
This article introduces a systematic methodology to design microarchitectures that are reconfigurable down to the pipeline stage. Reconfigurable microarchitectures were showed to provide significant energy improvements in accelerators under wide-volt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1106f8106c02157d0d2eea8af2c0c420
https://doi.org/10.1109/tvlsi.2019.2950959
https://doi.org/10.1109/tvlsi.2019.2950959
Multiplication is one of the widely used arithmetic operations in a variety of applications, such as image/video processing and machine learning. FPGA vendors provide high-performance multipliers in the form of DSP blocks. These multipliers are not o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b5cabeaacde136ce8bd2cf05dccc9016
https://tud.qucosa.de/id/qucosa:83401
https://tud.qucosa.de/id/qucosa:83401
Publikováno v:
IGARSS
This paper introduces the hardware design and implementation of Omega-K imaging algorithm. Based on the analysis of Omega-K algorithm theoretical derivation, we plan to use pipeline structure and soft IP multiplexed method to speed up the imaging spe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a0d9a6bba1c30957892396d25aedcd3
https://doi.org/10.1109/igarss47720.2021.9553776
https://doi.org/10.1109/igarss47720.2021.9553776
Publikováno v:
2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus).
Soft programmable IP-cores are usually used to speed up the integrated circuits design in FPGA. Soft blocks are formed from programmable logical FPGA elements independently from specific location on the FPGA and do not have pre-routed paths. Some FPG
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44d9b24835a7c9bd17441cf2a0a9d2d2
https://doi.org/10.1109/elconrus51938.2021.9396572
https://doi.org/10.1109/elconrus51938.2021.9396572
Autor:
Soon Ee Ong, Sje Yin Teo
Publikováno v:
ATS
Implementing artificial neural network (ANN) on hardware, e.g. as hard IP in SoC or soft IP in FPGA, for acceleration is one of the common methods to obtain high performance. Being the heart of ANN, the performance of artificial neuron directly deter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92e78c10c35d27e202cfe7365759ebfd
https://doi.org/10.1109/ats49688.2020.9301543
https://doi.org/10.1109/ats49688.2020.9301543
Publikováno v:
International Journal of Information Technology. 11:795-798
Latest FPGA devices integrate processor, DSP blocks and memories as IP cores, due to which it is possible to build high performance FPGA based embedded applications. As all these hard and soft IP blocks are integrated on a single FPGA chip, the syste
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a82cdc1dd7ae03b16a8e073527764bf5
https://doi.org/10.1007/s41870-018-0193-1
https://doi.org/10.1007/s41870-018-0193-1
Autor:
Deshya Wijesundera, Alok Prakash, Kisaru Liyanage, Kushagra Shah, Thilina Perera, Thambipillai Srikanthan
Publikováno v:
Applied Reconfigurable Computing. Architectures, Tools, and Applications ISBN: 9783030445331
ARC
ARC
This work proposes a novel technique for hardware area-time estimation of applications on FPGA. The application C code is first converted to the target independent LLVM IR prior to wrapping the basic blocks as functions using a LLVM transformation pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::492c2842791e2ec1aadb1e08ae901c80
https://doi.org/10.1007/978-3-030-44534-8_13
https://doi.org/10.1007/978-3-030-44534-8_13
Publikováno v:
HPEC
Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) mainly due to economic motivations. However, allowing third-party involvement also increases the possibility of malicious attacks, such as ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad3d55111621868c29430941c1e6319a
https://doi.org/10.1109/hpec.2019.8916225
https://doi.org/10.1109/hpec.2019.8916225