Zobrazeno 1 - 10
of 101
pro vyhledávání: '"Snorre Aunet"'
Publikováno v:
IEEE Access, Vol 10, Pp 30624-30642 (2022)
SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy ef
Externí odkaz:
https://doaj.org/article/60bc6d27adf24f3bb8294e76681faf18
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:2687-2691
We propose architectural advances in low voltage, energy-efficient, level shifters. A write assist circuit is introduced, to support the up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage current in split sig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab481db4f788abdaa8ba0875b2ff0472
https://doi.org/10.1109/tcsii.2020.2966654
https://doi.org/10.1109/tcsii.2020.2966654
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:2223-2227
This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fa1d4c08819c5e56fe486bc84e796f8
https://doi.org/10.1109/tvlsi.2020.3013139
https://doi.org/10.1109/tvlsi.2020.3013139
Publikováno v:
2021 IEEE 20th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91d3035074f81b18bfa62eaca9bef8d4
https://doi.org/10.1109/powermems54003.2021.9658410
https://doi.org/10.1109/powermems54003.2021.9658410
Publikováno v:
NorCAS
This study aims at comparing two subthreshold flip-flop architectures in frequency divider applications, implemented and fabricated in 130 nm CMOS process technology. They are the Power PC (Performance Computing) and Nand race-free flip-flops. Identi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32e26991a7f0c805deb4ffec787231b9
https://doi.org/10.1109/norcas53631.2021.9599871
https://doi.org/10.1109/norcas53631.2021.9599871
Autor:
Snorre Aunet
Publikováno v:
NEWCAS
Logic and memory proven in silicon, operating at sub-100 mV V dd s are discussed. Static CMOS is likely to be augmented with Schmitt-trigger based solutions, especially for memories that should operate at V dd s below 100 mV.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6a6f25a2c1c16b7a99acf9781337147
https://doi.org/10.1109/newcas50681.2021.9462735
https://doi.org/10.1109/newcas50681.2021.9462735
Publikováno v:
Journal of Signal Processing Systems
Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, supp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a42fdc7817a40d8b2a7f361e592be3b3
https://hdl.handle.net/11250/2986608
https://hdl.handle.net/11250/2986608
Publikováno v:
NorCAS
This study presents a comparative study of single, regular and flip well subthreshold SRAMs in 22 nm FDSOI technology. A 7T loadless SRAM cell with a decoupled read and write port has been used as a case study. Simulation results, based on the extrac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb82a64f33eb3d0a1bf0a177c9e3bc1b
https://doi.org/10.1109/norcas51424.2020.9265001
https://doi.org/10.1109/norcas51424.2020.9265001
Publikováno v:
NorCAS
This paper designs and reports energy efficient subthreshold adders using 22 nm FDSOI technology. The dynamic body biasing technique and multi-threshold voltage devices have been used to match Pull up/Pull down networks (PUN/PDN). The post-layout sim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f74208da95462fea19436c3e5a08d12e
https://doi.org/10.1109/norcas51424.2020.9265131
https://doi.org/10.1109/norcas51424.2020.9265131
Publikováno v:
Microprocessors and Microsystems. 56:92-100
Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, the functional yield of CMOS logic gates and minimize the leakage energy per cycle in the subthreshold region. In this work, the PMOS/NMOS strength ratio w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a2f104b1a78da7ddaf29df45ccbb52f
https://doi.org/10.1016/j.micpro.2017.11.002
https://doi.org/10.1016/j.micpro.2017.11.002