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pro vyhledávání: '"Small Outline Integrated Circuit"'
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Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:1223-1234
Under a given set of boundary conditions (BCs), the thermal performance of an electronic system is generally evaluated based on its steady-state response to constant power loads and thermal BCs that are time-averaged values of the actual transient or
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72c7e57bcbe6fb30526634841de902d6
https://doi.org/10.1109/tcpmt.2021.3089982
https://doi.org/10.1109/tcpmt.2021.3089982
Publikováno v:
2021 22nd International Conference on Electronic Packaging Technology (ICEPT).
Data-centric computing including data analytics, machine learning and AI is the main driving force for high-end performance 3D microelectronic packaging. TSV -based technology has enabled the Foveros 3D packaging from Intel, the 3D system integration
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9eb60975113dcbc9b023fa085f1f95b4
https://doi.org/10.1109/icept52650.2021.9567982
https://doi.org/10.1109/icept52650.2021.9567982
Autor:
Beng Kuan Lim, Cheok Io Fong
Publikováno v:
2021 IEEE Regional Symposium on Micro and Nanoelectronics (RSM).
Quad Flat No lead (QFN) is a common package, which widely uses in the semiconductor industry. It has high advantage of low cost, flexible size and footprint, good heat dissipation with ability to have die attach paddle (DAP) expose and lower electric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::078dd44a8c6ddc4cd1cc4d7381bf7093
https://doi.org/10.1109/rsm52397.2021.9511579
https://doi.org/10.1109/rsm52397.2021.9511579
Autor:
Be-nazir Khan
Publikováno v:
International Symposium on Microelectronics. 2019:000545-000549
A detailed computational fluid dynamic based thermal model and simulation of exposed pad SOIC package on PCB is developed with Nano and gold-based material to characterize the thermal behavior or cooling capability of the package. Achieving lower the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c13998a89582c72e010942da2b48644e
https://doi.org/10.4071/2380-4505-2019.1.000545
https://doi.org/10.4071/2380-4505-2019.1.000545
Autor:
Frank J.C. Lee
Publikováno v:
ISPD
Heterogeneous three-dimensional (3-D) package-level integration plays an increasingly important role in the design of higher functional density and lower power processors for general computing, machine learning and mobile applications. In TSMC's 3DFa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf25138ac034e9ba58338ed1bc86c780
https://doi.org/10.1145/3439706.3446881
https://doi.org/10.1145/3439706.3446881
Autor:
Dogan Ibrahim
Publisher Summary The term “microcomputer” is used to describe a system that includes a minimum of a microprocessor, program memory, data memory, and input/output (I/O). Some microcomputer systems include additional components such as timers, cou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f780b5c43589e9a55c3bfa2ceb6544dc
https://doi.org/10.1016/b978-0-12-821227-1.00001-3
https://doi.org/10.1016/b978-0-12-821227-1.00001-3
Autor:
Chen Chih-Lin, Cheng Yun-Wei, K.-J. Chen, Douglas Yu, C.H. Tsai, Tsung-Ching Huang, M. F. Chen, C. T. Wang, F. Lee, J. Yuan
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ebc0c91e4ee8f39a6a09c3d828ff843
https://doi.org/10.1109/iedm13553.2020.9372005
https://doi.org/10.1109/iedm13553.2020.9372005
Autor:
Chan Pin Chong
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
The growth of advance packaging especially with Heterogeneous integration and 3D stacking, starting with EMIB (Embedded Multi-die Interconnect Bridge), inFO and CoWoS (Chip-on-Wafer-on-Substrate), Foveros, SoIC (System-on-Integrated Chips) and (3D Mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::599717bcb2514c215d46a39a5907fd81
https://doi.org/10.1109/eptc50525.2020.9315100
https://doi.org/10.1109/eptc50525.2020.9315100
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
An ultrahigh density 3D technology, SoIC_UHD, with sub-micron pitch inter-chip vertical interconnect enabling a density ≥ 1.2 million bonds/mm2 is reported for the first time. Proven yield and reliability of SoIC_UHD are demonstrated with a foundry
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12afb6958fddb42be5759aa29eb8762b
https://doi.org/10.1109/ectc32862.2020.00096
https://doi.org/10.1109/ectc32862.2020.00096