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pro vyhledávání: '"Small Outline Integrated Circuit"'
Akademický článek
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Conference
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Autor:
Ivan T. Gil Costa, Allen M. Menor, Alvin B. Denoyo, Ton C. Pinili, Rod J. Delos Santos, Darwin J. De Lazo
Publikováno v:
2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT).
In response to the need in the semiconductor industry to have a higher moisture sensitivity level (MSL) satisfying the no delamination criteria in all interfaces for automotive devices with a reasonable cost are the main objectives in this study. To
Conference
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Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:1223-1234
Under a given set of boundary conditions (BCs), the thermal performance of an electronic system is generally evaluated based on its steady-state response to constant power loads and thermal BCs that are time-averaged values of the actual transient or
Autor:
Beng Kuan Lim, Cheok Io Fong
Publikováno v:
2021 IEEE Regional Symposium on Micro and Nanoelectronics (RSM).
Quad Flat No lead (QFN) is a common package, which widely uses in the semiconductor industry. It has high advantage of low cost, flexible size and footprint, good heat dissipation with ability to have die attach paddle (DAP) expose and lower electric
Autor:
Dogan Ibrahim
Publisher Summary The term “microcomputer” is used to describe a system that includes a minimum of a microprocessor, program memory, data memory, and input/output (I/O). Some microcomputer systems include additional components such as timers, cou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f780b5c43589e9a55c3bfa2ceb6544dc
https://doi.org/10.1016/b978-0-12-821227-1.00001-3
https://doi.org/10.1016/b978-0-12-821227-1.00001-3
Publikováno v:
2021 22nd International Conference on Electronic Packaging Technology (ICEPT).
Data-centric computing including data analytics, machine learning and AI is the main driving force for high-end performance 3D microelectronic packaging. TSV -based technology has enabled the Foveros 3D packaging from Intel, the 3D system integration
Autor:
Be-nazir Khan
Publikováno v:
International Symposium on Microelectronics. 2019:000545-000549
A detailed computational fluid dynamic based thermal model and simulation of exposed pad SOIC package on PCB is developed with Nano and gold-based material to characterize the thermal behavior or cooling capability of the package. Achieving lower the
Autor:
Frank J.C. Lee
Publikováno v:
ISPD
Heterogeneous three-dimensional (3-D) package-level integration plays an increasingly important role in the design of higher functional density and lower power processors for general computing, machine learning and mobile applications. In TSMC's 3DFa