Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Siying Feng"'
Autor:
Siying Feng, Renxi Gu
Publikováno v:
Proceedings of Business and Economic Studies. 5:73-78
Under the perspective of China’s economic transformation and upgrading, foreign trade is facing pressure from the transformation of internal economic capacity and external trade environment. It is urgent to explore new paths and directions, in orde
Autor:
Xin He, Kuan-Yu Chen, Siying Feng, Hun-Seok Kim, David Blaauw, Ronald Dreslinski, Trevor Mudge
Publikováno v:
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques.
Autor:
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor Mudge, Ronald Dreslinski, Hun-Seok Kim, David Blaauw
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
Siying Feng, Xin He, Kuan-Yu Chen, Liu Ke, Xuan Zhang, David Blaauw, Trevor Mudge, Ronald Dreslinski
Publikováno v:
Proceedings of the 49th Annual International Symposium on Computer Architecture.
Autor:
Chaitali Chakrabarti, Trevor Mudge, Dong-Hyeon Park, Subhankar Pal, Ronald G. Dreslinski, David Blaauw, Aporva Amarnath, Jonathan Beaumont, Chun Zhao, Austin Rovinski, Jielun Tan, Siying Feng, Hun-Seok Kim, Kuan-Yu Chen, Timothy Wesley, Michael Taylor, Paul Gao, Shaolin Xie
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:933-944
A sparse matrix–matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40-nm CMOS. The compute fabric consists of dedicated floating-point multiplication units, and general-purpos
Autor:
Chaitali Chakrabarti, Dong-Hyeon Park, Kuba Kaszyk, Trevor Mudge, Ronald G. Dreslinski, Michael O'Boyle, Magnus Morton, Xin He, Jiawen Sun, Siying Feng, Subhankar Pal, Murray Cole
Publikováno v:
Feng, S, Sun, J, Pal, S, He, X, Kaszyk, K, Park, D, Morton, M, Mudge, T, Cole, M, O'Boyle, M, Chakrabarti, C & Dreslinski, R 2021, CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics . in 2021 58th ACM/IEEE Design Automation Conference (DAC) . pp. 949-955, 58th Design Automation Conference, San Francisco, California, United States, 5/12/21 . https://doi.org/10.1109/DAC18074.2021.9586114
DAC
DAC
Sparse matrix-vector multiplication (SpMV) is a critical building block for iterative graph analytics algorithms. Typically, such algorithms have a varying active vertex set across iterations. This variability has been used to improve performance by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b42d472f35e3a285b2846edf6c3ef531
https://www.pure.ed.ac.uk/ws/files/199764078/CoSPARSE_FENG_DOA28022021_AFV.pdf
https://www.pure.ed.ac.uk/ws/files/199764078/CoSPARSE_FENG_DOA28022021_AFV.pdf
Autor:
Ronald G. Dreslinski, Siying Feng, Christophe Dubach, Michael O'Boyle, Subhankar Pal, Aporva Amarnath
Publikováno v:
MICRO
Pal, S, Amarnath, A, Feng, S, O'Boyle, M, Dreslinski, R & Dubach, C 2021, SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator . in The 54th Annual IEEE/ACM International Symposium on Microarchitecture Proceedings . pp. 1005-1021, 54th IEEE/ACM International Symposium on Microarchitecture, Athens, Greece, 18/10/21 . https://doi.org/10.1145/3466752.3480134
Pal, S, Amarnath, A, Feng, S, O'Boyle, M, Dreslinski, R & Dubach, C 2021, SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator . in The 54th Annual IEEE/ACM International Symposium on Microarchitecture Proceedings . pp. 1005-1021, 54th IEEE/ACM International Symposium on Microarchitecture, Athens, Greece, 18/10/21 . https://doi.org/10.1145/3466752.3480134
Dynamic adaptation is a post-silicon optimization technique that adapts the hardware to workload phases. However, current adaptive approaches are oblivious to implicit phases that arise from operating on irregular data, such as sparse linear algebra
Autor:
Subhankar Pal, Ronald G. Dreslinski, Trevor Mudge, Siying Feng, Murray Cole, Kuba Kaszyk, Björn Franke, Michael O'Boyle
Publikováno v:
IISWC
Pal, S, Kaszyk, K, Feng, S, Franke, B, Cole, M, O'Boyle, M F P, Mudge, T & Dreslinski, R G 2020, HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework . in 2020 IEEE International Symposium on Workload Characterization (IISWC) . Institute of Electrical and Electronics Engineers (IEEE), pp. 13-24, 2020 IEEE International Symposium on Workload Characterization, Virtual Conference, 27/10/20 . https://doi.org/10.1109/IISWC50251.2020.00011
Pal, S, Kaszyk, K, Feng, S, Franke, B, Cole, M, O'Boyle, M F P, Mudge, T & Dreslinski, R G 2020, HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework . in 2020 IEEE International Symposium on Workload Characterization (IISWC) . Institute of Electrical and Electronics Engineers (IEEE), pp. 13-24, 2020 IEEE International Symposium on Workload Characterization, Virtual Conference, 27/10/20 . https://doi.org/10.1109/IISWC50251.2020.00011
The rising complexity of large-scale heterogeneous architectures, such as those composed of off-the-shelf processors coupled with fixed-function logic, has imposed challenges for traditional simulation methodologies. While prior work has explored tra
Autor:
Subhankar Pal, Kyle May, Aporva Amarnath, Chaitali Chakrabarti, Ronald G. Dreslinski, Siying Feng, Xin He, Trevor Mudge, Jiawen Sun, Chi-Sheng Yang, Kuba Kaszyk, John Magnus Morton, Sung Kim, Michael O'Boyle, Hun-Seok Kim, David Blaauw, Jonathan Beaumont, Dong-Hyeon Park, Murray Cole, Yan Xiong
Publikováno v:
PACT
Pal, S, Feng, S, Park, D, Kim, S, Amarnath, A, Yang, C-S, He, X, Beaumont, J, May, K, Xiong, Y, Kaszyk, K, Morton, J M, Sun, J, O'Boyle, M, Cole, M, Chakrabarti, C, Blaauw, D, Kim, H-S, Mudge, T & Dreslinski, R 2020, Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration . in Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques . pp. 175-190, 29th International Conference on Parallel Architectures and Compilation Techniques, Virtual conference, 3/10/20 . https://doi.org/10.1145/3410463.3414627
Pal, S, Feng, S, Park, D, Kim, S, Amarnath, A, Yang, C-S, He, X, Beaumont, J, May, K, Xiong, Y, Kaszyk, K, Morton, J M, Sun, J, O'Boyle, M, Cole, M, Chakrabarti, C, Blaauw, D, Kim, H-S, Mudge, T & Dreslinski, R 2020, Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration . in Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques . pp. 175-190, 29th International Conference on Parallel Architectures and Compilation Techniques, Virtual conference, 3/10/20 . https://doi.org/10.1145/3410463.3414627
With the end of Dennard scaling and Moore’s law, it is becoming increasingly difficult to build hardware for emerging applications that meet power and performance targets, while remaining flexible and programmable for end users. This is particularl
Autor:
Dong-Hyeon Park, Austin Rovinski, Aporva Amarnath, Yuhan Chen, Siying Feng, Subhankar Pal, Ronald G. Dreslinski, Trevor Mudge, Haojie Ye, Xin He
Publikováno v:
ICS
While systolic arrays are widely used for dense-matrix operations, they are seldom used for sparse-matrix operations. In this paper, we show how a systolic array of Multiply-and-Accumulate (MAC) units, similar to Google's Tensor Processing Unit (TPU)