Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Sitaraman V. Iyer"'
Autor:
Syed Rubab, James Guthrie, Jing Wang, Clifford Ting, Ruslana Shulyzki, Aynaz Vatankhahghadim, Michael De Vita, Alireza Parsafar, Junhong Zhao, Noam Dolev, Sitaraman V. Iyer, Bahram Zand, Aleksey Tyshchenko, Mike Bichan, Eric Liu, Fulvio Spagna, Shaham Sharifian, Katya Tyshchenko
Publikováno v:
CICC
This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and
Autor:
Sitaraman V. Iyer, Hasnain Lakdawala
Publikováno v:
Circuits at the Nanoscale ISBN: 9781315218762
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e86b06103a8d3fbccad04afffe442096
https://doi.org/10.1201/9781315218762-28
https://doi.org/10.1201/9781315218762-28
Autor:
Edward Wang, Tom Wang, Rizwan Qureshi, Harry Muljono, Hubert Hsieh, Sitaraman V. Iyer, Wei Chen, Min Huang, Kalapi Roy-Neogi, Nagmohan Satti, Sujal Vora, Simon M. Tam
Publikováno v:
ISSCC
SkyLake-SP (Scalable Performance), code name SKX, is the next generation Xeon® server processor fabricated on the Intel® 14nm tri-gate CMOS technology with 11-metal layers [1,2]. The SKX processor family has three core-count configurations. Each SK
Autor:
Guluke Tong, Sitaraman V. Iyer, Mahalingam Nagarajan, Lasya R Munagala, Siddharth Katare, Yang Bangda
Publikováno v:
2014 International SoC Design Conference (ISOCC).
In clock and data recovery system of high speed IO, the phase of the clock for data sampler needs fine resolution control so that the incoming data can be sampled at a time point with the best signal-to-noise ratio. A phase interpolator (PI) is norma
Publikováno v:
Scopus-Elsevier
The rapid layout synthesis of microresonators from high-level engineering specifications is demonstrated. Functional parameters such as resonant frequency, quality factor, and displacement amplitude at resonance are satisfied while simultaneously min
Autor:
Arvind Kumar, Zuoguo Wu, Fulvio Spagna, Sitaraman V. Iyer, Mohiuddin Mazumder, James E. Jaussi, Beomtaek Lee
Publikováno v:
ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1.
This paper describes an accurate and efficient analysis methodology that enables circuit optimization directly guided by platform-level metric such as link eye margin. Prior to this work, such analysis was not feasible due to significant compute time
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
Autor:
Amanda Tran, Renuka Krishnamurthy, Luke Tong, Jeff Ou, Sitaraman V. Iyer, Xuguang Zhang, Kavitha Prasad, Sujatha Gowder, Doug Gambetta, Hendra Rustam, Yongping Fan, Mamatha Deshpande, John K. Wu, Ravindran Mohanavelu, Chien-chun Lin, Peter Kwok, Fulvio Spagna, Lidong Chen, Roan M. Nicholson, Marcus Pasquarella, Rohit Kumar
Publikováno v:
ISSCC
The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all,
Autor:
L.R. Carley, R.T. Unetich, E.J. Zacherl, Sitaraman V. Iyer, Hasnain Lakdawala, Rajarishi Sinha, D.F. Guillou, D.M. Gaugel
Publikováno v:
CICC
This paper presents a 1-axis vibration sensor that integrates hermetically sealed micromechanical structures and BiCMOS circuits. Close integration of the micromechanical structures with sense circuits, and an area-efficient sensing scheme lead to sm
Publikováno v:
Design, Test, Integration, and Packaging of MEMS/MOEMS 2002.
A methodology for combined modeling of capacitance and force 9in a multi-layer electrostatic comb is demonstrated in this paper. Conformal mapping-based analytical methods are limited to 2D symmetric cross-sections and cannot account for charge conce
Autor:
Sitaraman V. Iyer, Tamal Mukherjee
Publikováno v:
SPIE Proceedings.
Design of springs is a very important step in the design process of inertial sensor. A procedure for computing the sprint stiffness for any single-chain configuration of beams and a translator which converts beam-based schematic representation of ine