Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Siok Wei Lim"'
Autor:
Nakul Narang, Siok Wei Lim, Bruce Xu, Kee Hian Tan, Toan Pham, Wenfeng Zhang, Junho Cho, Geoff Zhang, Chi Fung Poon, Hongtao Zhang, Parag Upadhyaya, Winson Lin, Jin Namkoong, Yohan Frans, Ken Chang, Arianne Roldan
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:18-28
The design of a dual-mode, 19–58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5–29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear eq
Autor:
Chin Yang Koay, Kee Hian Tan, Nakul Narang, Yohan Frans, Siok Wei Lim, Hongyuan Zhao, Jay Im, Parag Upadhyaya, Ping-Chuan Chiang, Ken Chang, Arianne Roldan, Kok Lim Chan
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:2663-2678
This paper describes a 32.75-Gb/s voltage-mode transmitter (TX) with three-tap feed forward equalization that is fabricated in a 16-nm FinFET CMOS technology. The TX uses a dual regulator architecture to allow independent control of output swing, out
Autor:
Sai Lalith Chaitanya Ambatipudi, Ken Chang, Arianne Roldan, Hongyuan Zhao, Haibing Zhao, Yipeng Wang, Parag Upadhyaya, Yohan Frans, Kee Hian Tan, Nakul Narang, Ping-Chuan Chiang, Siok Wei Lim, Declan Carey
Publikováno v:
VLSI Circuits
This work reports a 112-Gb/s low power voltage-mode transmitter (TX) with four-tap feed forward equalization (FFE), designed and fabricated in 16nm FinFET technology. The design includes a hybrid impedance controller with dual regulator architecture
Autor:
Nakul Narang, Kee Hian Tan, Geoff Zhang, Siok Wei Lim, Chi Fung Poon, Toan Pham, Yohan Frans, Junho Cho, Jin Namkoong, Bruce Xu, Arianne Roldan, Ken Chang, Wenfeng Zhang, Hongtao Zhang, Winson Lin, Parag Upadhyaya
Publikováno v:
ISSCC
Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without significant increase in cost or power per bit. In order to mitigate the cost of infrastructure upgrad
Autor:
Hongyuan Zhao, Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Ken Chang, Chin Yang Koay, Nakul Narang, Siok Wei Lim, Arianne Roldan, Parag Upadhyaya
Publikováno v:
A-SSCC
This paper describes the design of a highly flexible voltage-mode transmitter with 3-tap Feed Forward Equalization fabricated in a 16nm CMOS technology. The transmitter uses a dual regulator architecture to allow for independent control of swing, com
Autor:
Xuewen Jiang, Kenny Hsieh, Jason Gong, Didem Turker, Siok Wei Lim, Jose Anup P, Jay Im, Arianne Roldan, Fu-Tai An, Vassili Kireev, Ken Chang, Parag Upadhyaya, Daniel Wu, Jafar Savoj
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:2582-2594
This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages
Autor:
Bruce Xu, Ade Bekele, Jafar Savoj, Hiva Hedayati, Fu-Tai An, Parag Upadhyaya, Hesam Aslanzadeh, Jose Anup P, Yohan Frans, Toan Pham, Stanley Chen, Didem Furker, Daniel Wu, Siok Wei Lim, Jay Im, Ken Chang
Publikováno v:
ISSCC
The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have bee