Výsledky vyhledávání - "Simone M. Dartizio"

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Autor: Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Publikováno v: IEEE Journal of Solid-State Circuits. 58:634-646

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6802fed3b5523c68c56c2837d7ae85bf
https://doi.org/10.1109/jssc.2022.3228899

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Phase Noise Analysis of Periodically ON/OFF Switched Oscillators

Autor: Giacomo Castoro, Simone M. Dartizio, Andrea L. Lacaita, Salvatore Levantino

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 70:54-63

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2da984cdeb07c4ccb900339402f53b64
https://doi.org/10.1109/tcsi.2022.3211177

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A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

Autor: Francesco Tesolin, Simone M. Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Publikováno v: IEEE Journal of Solid-State Circuits. :1-12

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d9d56ea0f312ac946a2c6efb088c6f01
https://doi.org/10.1109/jssc.2023.3272483

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4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Autor: Giacomo Castoro, Simone M. Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Publikováno v: 2023 IEEE International Solid- State Circuits Conference (ISSCC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::02c1f35fc84a13304b66cdd22fed8efb
https://doi.org/10.1109/isscc42615.2023.10067351

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4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Autor: Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertuless, Carlo Samor, Andrea L. Lacaita, Salvatore Levantino

Publikováno v: 2023 IEEE International Solid- State Circuits Conference (ISSCC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::80298354b3af412da6edf46e0edb0026
https://doi.org/10.1109/isscc42615.2023.10067719

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A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler

Autor: Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Publikováno v: 2022 IEEE Custom Integrated Circuits Conference (CICC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eb1cfb02c446f02d9d73c302440d88a8
https://doi.org/10.1109/cicc53496.2022.9772796

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A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

Autor: Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1dfd96a7018090fb75b6789e3eb1a1f6
http://hdl.handle.net/11311/1221889

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32.3 A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter

Autor: Alessio Santiccioli, Salvatore Levantino, Francesco Tesolin, Michael Peter Kennedy, Angelo Parisi, Andrea L. Lacaita, Abanob Shehata, Luca Avallone, Luca Bertulessi, Simone M. Dartizio, Saleh Karman, Francesco Buccoleri, Carlo Samori, Mario Mercandelli

Publikováno v: ISSCC

The advent of the next-generation wireless communication standards demands increasingly faster transceivers, posing extremely challenging requirements on the frequency-synthesizer integrated jitter [1, 2]. As demonstrated in [1], the bang-bang digita

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::11af221677e4ca335aeed2d3915270c4
https://doi.org/10.1109/isscc42613.2021.9365768

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A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

Autor: Angelo Parisi, Alessio Santiccioli, Francesco Tesolin, Saleh Karman, Luca Avallone, Simone M. Dartizio, Andrea L. Lacaita, Abanob Shehata, Mario Mercandelli, Michael Peter Kennedy, Luca Bertulessi, Salvatore Levantino, Francesco Buccoleri, Carlo Samori

This work introduces a bang-bang fractional-N phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guar

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1beefc40ae39364ae98ece7def353ed0
http://hdl.handle.net/11311/1187540

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