Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Simon Reder"'
Autor:
Simon Reder, Jürgen Becker
Publikováno v:
RTAS
Computing tight upper bounds for the Worst-Case Execution Time (WCET) at design-time is a crucial step when developing hard real-time software. For multi-core processors, however, timing interference between processor cores is a major problem, which
Autor:
Jürgen Becker, Simon Reder
Publikováno v:
DATE
High performance demands of present and future embedded applications increase the need for multi-core processors in hard real-time systems. Challenges in static multi-core WCET-analysis and the more complex design of parallel software, however, oppos
Autor:
Harald Bucher, Simon Reder, Panayiotis Alefragis, Steven Derrien, Peer Ulbig, David Mueller, Jürgen Becker, Christian Ferdinand, Oliver Oey, Timo Stripf, Clément David, Fabian Kempf, Umut Durak, Nikolaos S. Voros, Isabelle Puaut, Stefanos Skalistis
Publikováno v:
Journal of Aerospace Information Systems
Journal of Aerospace Information Systems, 2019, 16 (11), pp.521-533. ⟨10.2514/1.I010749⟩
Journal of aerospace information systems, 16 (11), 521-533
Journal of Aerospace Information Systems, American Institute of Aeronautics and Astronautics, 2019, 16 (11), pp.521-533. ⟨10.2514/1.I010749⟩
Journal of Aerospace Information Systems, 2019, 16 (11), pp.521-533. ⟨10.2514/1.I010749⟩
Journal of aerospace information systems, 16 (11), 521-533
Journal of Aerospace Information Systems, American Institute of Aeronautics and Astronautics, 2019, 16 (11), pp.521-533. ⟨10.2514/1.I010749⟩
International audience; Multicore processing systems are the solution of choice to provide high embedded computing performance, but drawbacks in timing predictability and programmability limit their adoption in safety-critical aerospace applications.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7ab734abd2b75ccb531a3b2768ae7349
https://hal.science/hal-02383381/file/ARGO_JAIS_preprint.pdf
https://hal.science/hal-02383381/file/ARGO_JAIS_preprint.pdf
Autor:
Nikolaos S. Voros, Jürgen Becker, Christos Gogos, Christos Valouxis, Simon Reder, Umut Durak, Panayiotis Alefragis, Marcus Bednara, Merkourios Katsimpris, George Theodoridis, David Müller, George Goulas, Koray Kasnakli
Publikováno v:
Applied Reconfigurable Computing. Architectures, Tools, and Applications ISBN: 9783319788890
ARC
Applied Reconfigurable Computing. Architectures, Tools, and Applications-14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings
Lecture Notes in Computer Science
Lecture Notes in Computer Science-Applied Reconfigurable Computing. Architectures, Tools, and Applications
ARC
Applied Reconfigurable Computing. Architectures, Tools, and Applications-14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings
Lecture Notes in Computer Science
Lecture Notes in Computer Science-Applied Reconfigurable Computing. Architectures, Tools, and Applications
Using multi-core architectures for embedded time-critical systems creates a big challenge for developers due to the complexity of the underline mapping and scheduling problem. H2020 ARGO project [2] proposes a tool flow to minimize multi-core applica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::552db8677c969b386ff6b15d2e78b58e
https://doi.org/10.1007/978-3-319-78890-6_56
https://doi.org/10.1007/978-3-319-78890-6_56
Publikováno v:
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
DATE
DATE
Increasing performance requirements for cyber-physical systems in real-time applications raise the necessity to migrate to multi-core processor systems. However, commercial of the shelf multi-core systems are often inappropriate for the real-time dom
Autor:
Steven Derrien, Nikolaos S. Voros, Jürgen Becker, Simon Reder, Harald Bucher, Isabelle Puaut, Damien Hardy, Timon D. ter Braak, Panayiotis Alefragis, Christian Ferdinand, Angeliki Kritikakou, Imen Fassi, Umut Durak, Timo Stripf, Gerard Rauwerda, Clément David, Kim Sunesen, Martin Sicks, Marcus Bednara, Yann Debray
Publikováno v:
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
Design Automation and Test in Europe (DATE)
Design Automation and Test in Europe (DATE), 2017
Design Automation and Test in Europe (DATE), 2017, Mar 2017, Lausanne, Switzerland. pp.286-289, ⟨10.23919/DATE.2017.7927000⟩
DATE
Design Automation and Test in Europe (DATE)
Design Automation and Test in Europe (DATE), 2017
Design Automation and Test in Europe (DATE), 2017, Mar 2017, Lausanne, Switzerland. pp.286-289, ⟨10.23919/DATE.2017.7927000⟩
DATE
International audience; Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project 1 provides a programming paradigm and
Publikováno v:
DSD
We present a highly parallel SystemC RTL simulator with full delta cycle accuracy.Asynchronous and decentralized synchronization concept for many-core architectures.An automated tool-flow combines model analysis and parallel SystemC simulation.The an
Publikováno v:
SBCCI
Due to the growing complexity of embedded systems, simulation becomes an increasingly time-consuming task. Especially detailed simulation of so called Multi-Processor System-on-Chips (MPSoCs) is afflicted with extremely long runtimes and makes verifi
Publikováno v:
ReCoSoC
Raising the abstraction level or parallel execution are two possible solutions in order to cope with extremely long runtimes of complex Multi-Processor System-on-Chip (MPSoC) simulations. Within previous works, a SystemC/TLM based modeling methodolog
Autor:
Gokhan Erdogan, Harald Bucher, Oliver Sander, Simon Reder, Christoph Roth, Gabriel Marchesan Almeida, Jürgen Becker
Publikováno v:
ISSoC
The growing complexity of embedded applications currently causes a trend towards multi-core processors in the embedded domain. Time-consuming detailed simulations make the design of such systems increasingly sophisticated. In this work, applicability