Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Simon Lim Siak Boon"'
Autor:
Salahuddin Raju, Ravinder Pal Singh, Simon Lim Siak Boon, Ho Soon Wee, Sharon Lim Pei Siang, Soh Siew Boon
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
Fan-out Wafer Level Packaging is widely and commonly adopted to ease implementation for low-cost packaging. It offers an enhanced solution of standard wafer-level packaging (WLP), which gained popularity for its application in embedding integrated ci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e317d0e3b101b0e69490407bbe64f1c
https://doi.org/10.1109/eptc50525.2020.9315018
https://doi.org/10.1109/eptc50525.2020.9315018
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
Die attach and interconnect materials for power module device studied in this experiment included pressure-less sintering paste and SnSb solder. The initial evaluation on various pressure-less silver (Ag) sintering die attach pastes showed that type
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c50cbfb034366a09f4c379378c87b8c
https://doi.org/10.1109/eptc50525.2020.9315011
https://doi.org/10.1109/eptc50525.2020.9315011
Autor:
Simon Lim Siak Boon, Tai Chong Chai, Sharon Lim Pei Siang, Ser Choong Chong, Eva Wai Leong Ching
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Mobile application or appliance demands multi-functions, high speed, light or small form factor and low cost. One of the common approaches to meet all these requirement is put one package over another package. This approach is commonly known as Packa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::298a57b8d976d694fde997db4934559e
https://doi.org/10.1109/ectc32862.2020.00143
https://doi.org/10.1109/ectc32862.2020.00143
Autor:
Simon Lim Siak Boon, Xiaowu Zhang, Yong Han, Xiaobai Wang, Yosephine Andriani, Sharon Lim Pei Siang, Boon Long Lau, Ming Chinq Jong, Songlin Liu, Lin Bu
Publikováno v:
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC).
This paper presents an advanced modeling technology on wafer warpage after post mold curing (PMC) for the 12 inch mold-1st Fan-Out Wafer Level Packaging (FOWLP) with consideration of effects of viscoelastic model and chemical cure shrinkage, and laye
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35d58c54c3416427bfea16ed59f2bb82
https://doi.org/10.1109/eptc47984.2019.9026620
https://doi.org/10.1109/eptc47984.2019.9026620
Autor:
Serine Soh Siew Boon, Chai Tai Chong, Simon Lim Siak Boon, Sharon Lim Pei Shan, Hsiao Hsiang Yao, David Ho Soon Wee, Chong Ser Choong
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
This paper describes the process development of fan-out wafer level package (FO-WLP) package that uses mold encapsulation to form the antenna element. The FO-WLP package is designed with a target frequency of 60GHz for wireless local area network (WL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c22bbfa921553a88085dbb988c916ec0
https://doi.org/10.1109/eptc.2018.8654415
https://doi.org/10.1109/eptc.2018.8654415
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
This paper is presenting the fabrication of wafer substrate level chip-scale packaging process on MEMS. The key processes are to develop the over-mold wafer level chip-scale packaging solution for MEMS which using metal deposited silicon pillar and C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea95193db486aa0aa552dba6ccac1f76
https://doi.org/10.1109/eptc.2018.8654373
https://doi.org/10.1109/eptc.2018.8654373