Výsledky vyhledávání - "Simon J. Hollis"

Full custom design of an arbitrary waveform gate driver with 10 GHz waypoint rates for GaN FETs

Autor: Harry C. P. Dymond, Simon J. Hollis, Neville McNeill, Dinesh Pamunuwa, Bernard H. Stark, Jianjing Wang, Dawei Liu

Publikováno v: Liu, D, Dymond, H C P, Hollis, S J, Wang, J, Mcneill, J N, Stark, B H & Pamunuwa, I D B 2020, ' Full custom design of an arbitrary waveform gate driver with 10 GHz waypoint rates for GaN FETs ', IEEE Transactions on Power Electronics, pp. 8267-8279 . https://doi.org/10.1109/TPEL.2020.3044874

Active gate driving of power devices seeks to shape switching trajectories via the gate, for example, to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::aeeafa7ac470d9b66fef88b55fcb04c1
https://strathprints.strath.ac.uk/75186/1/Liu_etal_TPE_Full_custom_design_of_an_arbitrary_waveform_gate_driver.pdf

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A 6.7-GHz Active Gate Driver for GaN FETs to Combat Overshoot, Ringing, and EMI

Autor: Neville McNeill, Dinesh Pamunuwa, Bernard H. Stark, Harry C. P. Dymond, Jeremy J. O. Dalton, Simon J. Hollis, Jianjing Wang, Dawei Liu

Publikováno v: Dymond, H C P, Wang, J, Liu, D, Dalton, J J O, McNeill, N, Pamunuwa, D, Hollis, S J & Stark, B H 2018, ' A 6.7-GHz Active Gate Driver for GaN FETs to Combat Overshoot, Ringing, and EMI ', IEEE Transactions on Power Electronics, vol. 33, no. 1, 7880639, pp. 581-594 . https://doi.org/10.1109/TPEL.2017.2669879

Active gate driving has been demonstrated to beneficially shape switching waveforms in Si- and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limit

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::06badd1ae46cb0dcc2e677f6f5e0abe7
https://doi.org/10.1109/tpel.2017.2669879

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Building blocks for future dual-channel GaN gate drivers: Arbitrary waveform driver, bootstrap voltage supply, and level shifter

Autor: Jianjing Wang, Simon J. Hollis, Dawei Liu, Harry C. P. Dymond, Bernard H. Stark

Publikováno v: 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD).

Capitalising on the high-speed switching capability of 650 V GaN FETs in power-electronic bridge-legs is challenging. Whilst active gate driving has previously been shown to help overcome adverse switching behaviour, the best results are likely to be

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1e679c97cf67b6288ccc6905fa976bfd
https://doi.org/10.1109/ispsd.2019.8757646

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A new design technique for sub-nanosecond delay and 200 V/ns power supply slew-tolerant floating voltage level shifters for GaN SMPS

Autor: Bernard H. Stark, Dawei Liu, Simon J. Hollis

Publikováno v: Liu, D, Hollis, S & Stark, B 2019, ' A new design technique for sub-nanosecond delay and 200 V/ns power supply slew-tolerant floating voltage level shifters for GaN SMPS ', IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 66, no. 3, 8535039, pp. 1280-1290 . https://doi.org/10.1109/TCSI.2018.2878668

Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rate

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::abe117114929af6ef77fcae9520bdd68
https://research-information.bris.ac.uk/en/publications/11883e7f-d443-4c73-abce-466db01a35cf

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Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-impedance patterns

Autor: Dawei Liu, Jianjing Wang, Bernard H. Stark, Neville McNeill, Simon J. Hollis, Dinesh Pamunuwa, Jeremy J. O. Dalton, Harry C. P. Dymond

Publikováno v: Dymond, H C P, Liu, D, Wang, J, Dalton, J, McNeill, N, Pamunuwa, D, Hollis, S & Stark, B 2017, Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-impedance patterns . in 2016 IEEE Energy Conversion Congress and Exposition (ECCE 2016) : Proceedings of a meeting held 18-22 September 2016, Milwaukee, Wisconsin, USA ., 7855385, Institute of Electrical and Electronics Engineers (IEEE), pp. 5116-5122, 2016 IEEE Energy Conversion Congress and Exposition, ECCE 2016, Milwaukee, United States, 18/09/16 . https://doi.org/10.1109/ECCE.2016.7855385

Active gate driving provides an opportunity to reduce EMI in power electronic circuits. Whilst it has been demonstrated for MOS-gated silicon power semiconductor devices, reported advanced gate driving in wide-bandgap devices has been limited to a si

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::47b2cf37ea5cf2d69dfd7c46a1b4cdd9
https://research-information.bris.ac.uk/ws/files/86255188/Bernard_Stark_Reduction_of_oscillations_in_a_GaN_bridge_leg_using_active_gate_driving_with_sub_ns_resolution.pdf

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Shaping switching waveforms in a 650 V GaN FET bridge-leg using 6.7 GHz active gate drivers

Autor: Jianjing Wang, Harry C. P. Dymond, Dinesh Pamunuwa, Simon J. Hollis, Bernard H. Stark, Jeremy J. O. Dalton, Neville McNeill, Dawei Liu

Publikováno v: Dalton, J J O, Wang, J, Dymond, H C P, Liu, D, Pamunuwa, D, Stark, B H, McNeill, N & Hollis, S J 2017, Shaping Switching Waveforms in a 650 V GaN FET Bridge-Leg Using 6.7 GHz Active Gate Drivers . in 2017 IEEE Applied Power Electronics Conference and Exposition (APEC 2017) : Proceedings of a meeting held 26-30th March 2017, Tampa, FL, USA ., 7930970, Institute of Electrical and Electronics Engineers (IEEE), pp. 1983-1989, 32nd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2017, Tampa, United States, 26/03/17 . https://doi.org/10.1109/APEC.2017.7930970

The application of active gate driving to 40 V GaN FETs has previously been shown to reduce ringing and EMI-generating spectral content in the switch-node voltage waveforms. This paper, for the first time, shows active gate driving applied to 650 V G

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::52f5a98349d3be625c56ca9086298dd0
https://doi.org/10.1109/apec.2017.7930970

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Challenges for Energy Harvesting Systems Under Intermittent Excitation

Autor: Stephen G. Burrow, Simon J. Hollis, Guang Yang, Bernard H. Stark

Publikováno v: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 4:364-374

Energy harvesting is showing great promise for powering wireless sensors. However, under intermittent environmental power, low-power harvesting systems designed for stable conditions suffer reduced effectiveness or fail entirely. This work aims to im

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2f7acb97528ed2600e31fb300f121416
https://doi.org/10.1109/jetcas.2014.2337172

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eXtended Torus routing algorithm for networks‐on‐chip: a routing algorithm for dynamically reconfigurable networks‐on‐chip

Autor: Simon J. Hollis, Jose L Nunez-Yanez, Arash Farhadi Beldachi

Publikováno v: Farhadi Beldachi, A F, Hollis, S J & Nunez-Yanez, J L 2014, ' eXtended Torus routing algorithm for networks-on-chip : a routing algorithm for dynamically reconfigurable networks-on-chip ', IET Computers and Digital Techniques, vol. 8, no. 3, pp. 148-162 . https://doi.org/10.1049/iet-cdt.2013.0087

This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3829d105b1197c86312d0a5510876d24
https://doi.org/10.1049/iet-cdt.2013.0087

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Exploiting Emergence in On-Chip Interconnects

Autor: Radu Marculescu, Paul Bogdan, Christopher L. Jackson, Simon J. Hollis

Publikováno v: IEEE Transactions on Computers. 63:570-582

To solve the grand challenges in contemporary chip design, such as process-to-core mapping, energy reduction, and maintenance of programmer/hardware abstraction, we advocate for self-optimizing (emergent) networks-on-chip (NoC). In these networks, to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e095aeb542181f16c02b073e0e42e00d
https://doi.org/10.1109/tc.2012.273

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Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance

Autor: Dawei Liu, Neville McNeill, Bernard H. Stark, Harry C. P. Dymond, Simon J. Hollis

Publikováno v: Liu, D, Hollis, S J, Dymond, H C P, McNeill, N & Stark, B H 2016, ' Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance ', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 7, 7410045, pp. 688-692 . https://doi.org/10.1109/TCSII.2016.2530902

A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c0df42a304a41dc2e4f539dfc34ef53d
https://strathprints.strath.ac.uk/65298/1/Liu_etal_IEETCS2016_Design_of_370_ps_delay_floating_voltage_level_shifters.pdf

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