Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Simeon Realov"'
Autor:
Gregory K. Chen, Sanu Mathew, Amit Agarwal, Iqbal R. Rajwani, Steven K. Hsu, Mark A. Anders, Vikram B. Suresh, Simeon Realov, Knag Phil, Ram Krishnamurthy, Satish Damaraju, Vivek De, Monodeep Kar, Sumbul Huseyin Ekin, Himanshu Kaul, Raghavan Kumar
Publikováno v:
VLSI Circuits
Low-clock-power digital standard cell IPs in 10nm CMOS, featuring low-power shared-clock (LPSC) flip-flops (FFs), LPSC back-to-back (B2B) FFs, and pass-gate (PG) integrated clock gates (ICGs), achieve up to 14%, 45%, and 14% measured clock energy imp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::822cabc99162cbffba9266b137201b38
https://doi.org/10.1109/vlsicircuits18222.2020.9163007
https://doi.org/10.1109/vlsicircuits18222.2020.9163007
Autor:
Sanu Mathew, Gregory K. Chen, Vivek De, Mark A. Anders, Himanshu Kaul, Knag Phil, Monodeep Kar, Sumbul Huseyin Ekin, Raghavan Kumar, Simeon Realov, Amit Agarwal, Steven K. Hsu, Mahesh K. Kumashikar, Ram Krishnamurthy
Publikováno v:
ISSCC
Flip-flops (FFs) are key building blocks in high-performance microprocessors, discrete graphics, and hardware accelerators [1]–[3], where pushing frequency has become increasingly critical due to emerging applications, such as AI, machine learning,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6edda0de1627677108689887ab2cf09
https://doi.org/10.1109/isscc19947.2020.9062941
https://doi.org/10.1109/isscc19947.2020.9062941
Autor:
Kaizad Mistry, Simeon Realov, Yeoh Andrew W, Chin-Hsuan Chen, Ranjith Kumar, Ian R. Post, Ying Zhang, Tai-Hsuan Wu, Somashekar Bangalore Prakash, Madhavan Atul, Quan Shi, Xinning Wang, Peng Zheng, Gadigatla Srinivasa Chaitanya, Nabors Marni, Chris Portland Auth
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e47600e063f4c3676ee823f1726d2eed
https://doi.org/10.1109/iedm.2018.8614662
https://doi.org/10.1109/iedm.2018.8614662
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:867-880
A fully-integrated single-photon avalanche diode (SPAD) and time-to-digital converter (TDC) array for high-speed fluorescence lifetime imaging microscopy (FLIM) in standard 130 nm CMOS is presented. This imager is comprised of an array of 64-by-64 SP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06e78184ef94926843e165ca103bc647
https://doi.org/10.1109/jssc.2013.2293777
https://doi.org/10.1109/jssc.2013.2293777
Autor:
Kenneth L. Shepard, Simeon Realov
Publikováno v:
IEEE Transactions on Electron Devices. 60:1716-1722
An on-chip variability characterization system implemented in a 45-nm CMOS process is used for direct time-domain measurements of random telegraph noise (RTN) in small-area devices. A procedure for automated extraction of RTN parameters from large vo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e3ce5baf3924259b74fc41130c11fec
https://doi.org/10.1109/ted.2013.2254118
https://doi.org/10.1109/ted.2013.2254118
Autor:
Simeon Realov, Kenneth L. Shepard
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:814-826
An on-chip system for combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f74410949bdd40662e364406def2b70d
https://doi.org/10.1109/jssc.2013.2237695
https://doi.org/10.1109/jssc.2013.2237695
Publikováno v:
2012 IEEE International Conference on Microelectronic Test Structures.
We present a simple test structure to measure C-V and I-V curves of the same nominal size FET. The structure is simple enough to be used for technology development, requires only first metal for routing, and allows parallel test. It is an extension o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eec67223bfbae7d62c528812c970875d
https://doi.org/10.1109/icmts.2012.6190656
https://doi.org/10.1109/icmts.2012.6190656
Autor:
Simeon Realov, Kenneth L. Shepard
Publikováno v:
2010 International Electron Devices Meeting.
RTN measurements in 45-nm CMOS across device bias and geometry using an on-chip characterization system are reported. An automated methodology for extracting RTN levels, amplitude and dwell times is developed. Complex RTN magnitude is statistically m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64ce5513680b3c0243684b922d4bdf15
https://doi.org/10.1109/iedm.2010.5703436
https://doi.org/10.1109/iedm.2010.5703436
Publikováno v:
ISQED
An on-chip test-and-measurement system with digital interfaces that can perform device-level characterization of large-dense arrays of transistors is demonstrated in 90- and 65-nm technologies. The collected variability data from the 90-nm run is use
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::07ed1f1193647a0ab024c0778201cf41
https://doi.org/10.1109/isqed.2009.4810288
https://doi.org/10.1109/isqed.2009.4810288