Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Sigang Ryu"'
Publikováno v:
Proceedings of the Great Lakes Symposium on VLSI 2023.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::248d043dbbc034b2e8b83edb2120656e
https://doi.org/10.1145/3583781.3590212
https://doi.org/10.1145/3583781.3590212
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:2876-2889
This paper presents a new time-based pipelined analog-to-digital converter (ADC) with multiplying-DAC (MDAC) stages capable of robust $2 \times $ residue amplification by subtracting two pulse widths. First, the input voltage is converted into two ti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe052994e9d43d6585844f25564e0264
https://doi.org/10.1109/tcsi.2021.3079338
https://doi.org/10.1109/tcsi.2021.3079338
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:2823-2832
A 2 $\times $ blind-oversampling, fractionally spaced equalizer (FSE) receiver is presented as an effective way to combine adaptive equalization and timing recovery in a single control loop. To additionally support plesiochronous clocking, the presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f48e59e1681eb8e29988935fffc276d
https://doi.org/10.1109/jssc.2019.2919417
https://doi.org/10.1109/jssc.2019.2919417
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:1245-1257
This paper presents a novel spread-spectrum clock (SSC) tracking aid for digitally-controlled clock and data recovery (CDR) loops. The proposed tracking aid accurately recovers the time instants when the slope of the incoming data frequency ramp chan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50f17c45dbd0ce185cf1fc478ad2959c
https://doi.org/10.1109/tcsi.2018.2879614
https://doi.org/10.1109/tcsi.2018.2879614
Publikováno v:
A-SSCC
A 2× blind-oversampling, fractionally-spaced equalizer (FSE) receiver is presented as an effective way to combine adaptive equalization and infinite-range timing recovery. A FSE can perform equalization as well as timing adjustment via data-interpol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87b8deffe389b7873be7d68d076e4642
https://doi.org/10.1109/asscc.2018.8579286
https://doi.org/10.1109/asscc.2018.8579286
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:1773-1784
A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5682b74cef7999a24df23db85a582c3b
https://doi.org/10.1109/jssc.2014.2312412
https://doi.org/10.1109/jssc.2014.2312412
Publikováno v:
ISSCC
To obtain a 20cm-resolution image within a 15m distance using an X-band FMCW radar, an agile chirp frequency synthesizer phase-locked loop (FSPLL) with a wide chirp bandwidth (BW) greater than 750MHz and a short chirp period (Tm) less than 100µs is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2512f7cdba4d2454ecb1bcd05db3eb24
https://doi.org/10.1109/isscc.2016.7417995
https://doi.org/10.1109/isscc.2016.7417995
Publikováno v:
CICC
This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLL's second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db2366ada9c94d732ecf8dc50e9522d1
https://doi.org/10.1109/cicc.2013.6658470
https://doi.org/10.1109/cicc.2013.6658470
Publikováno v:
ISCAS
A model-first flow is demonstrated for designing and validating a high-speed serial receiver in a digital TV. Starting with a functional model of the top-level mixed-signal system rather than with transistor-level designs helps detect problems due to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::baed4a76c3d415a8ed372e4d987dbf4a
https://doi.org/10.1109/iscas.2012.6272147
https://doi.org/10.1109/iscas.2012.6272147