Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Sidhartha Sankar Rout"'
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. :1-16
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40:2372-2385
The contemporary Network on Chips (NoCs) are becoming intricate in design to serve the high throughput and low latency demands of multicore platforms. The complexity level of interconnect module makes it extremely difficult to ensure the functional c
Publikováno v:
ACM Journal on Emerging Technologies in Computing Systems.
Wireless Network-on-Chip (WNoC) requires a Medium Access Control (MAC) mechanism for an interference free sharing of the wireless channel. In traditional MAC, a token is circulated among the Wireless Interfaces (WIs) in a Round Robin manner. The WI w
Publikováno v:
Frontiers of Quality Electronic Design (QED) ISBN: 9783031163432
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4053892a1d02644682a16350387d1a81
https://doi.org/10.1007/978-3-031-16344-9_15
https://doi.org/10.1007/978-3-031-16344-9_15
Publikováno v:
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 11:278-291
Flooding-based Denial-of-service (DoS) attacks have been prevalent in Network-on-Chip (NoC) architectures, due to its shared nature and open access to all the on-chip modules. A Malicious Intellectual Property (MIP) within a System-on-Chip (SoC) crea
Publikováno v:
Network-on-Chip Security and Privacy ISBN: 9783030691301
Network-on-Chip (NoC) is popularly used for interconnecting multiple cores in modern System-on-Chips (SoCs). The design intricacy of NoC is growing with the increasing complexity of SoCs. This results in multiple bugs being present on the interconnec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::176a8f166bd47b7f834d9d9ce76a6158
https://doi.org/10.1007/978-3-030-69131-8_13
https://doi.org/10.1007/978-3-030-69131-8_13
Publikováno v:
ISCAS
Wireless Network-on-Chip (WNoC) broadly adopts single channel for low overhead data transmission. Sharing of the channel among multiple wireless interfaces (WIs) is controlled by a channel access mechanism (CAM). Such CAM can be malfunctioned by a Ha
Publikováno v:
ASP-DAC
The contemporary network-on-chips (NoCs) are so complex that capturing all network functional faults at presilicon verification stage is nearly impossible. So, on-chip design-for-debug (DfD) structures such as trace buffers are provided to assist cap
Publikováno v:
iSES
The current hardware verification techniques make use of pseudo-random number generators to induce test inputs. However, the randomization of some inputs can lead to an unexpected output, thereby causing failures. These failures are usually debugged
Publikováno v:
SoCC
The contemporary network-on-chips (NoCs) have highly complex architectures. So, robust post-silicon validation mechanism is required for error-proof NoC design. Traces of packet transactions are generated during NoC validation and are stored for faul