Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Siddhesh Darne"'
Autor:
Jong Yuh, Jason Li, Heguang Li, Yoshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, David Han, Masatoshi Okumura, Jiwen Liu, John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Aki Matsuda, Chakshu Puri, Chen Chen, Indra K V, Chaitanya G, Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, Farookh Moogat, In-Soo Yoon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Takashi Shigeoka, Kosuke Yanagidaira, Takuyo Kodama, Ryo Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Siddhesh Darne, Teruo Takagiwa, Junya Matsuno, Yuki Shimizu, Naoya Tokiwa, Kei Shiraishi, Tetsuaki Utsumi, Hiroyuki Mizukoshi, Koji Hosono, Masatsugu Kojima, Junji Musha, Takuyo Kodama, Osamu Kobayashi, Masahiro Kano, Takeshi Hioka, Naoki Ookuma, Yuki Kuniyoshi, Takahiro Sugimoto, Ryoichi Tachibana, Hiroshi Sugawara, Hiroki Date, Kazuhide Yoneya, Srinivas Rajendra, Akira Arimizu, Yoshito Katano, Mitsuhiro Abe, Keiji Tsunoda, Masakazu Ehama, Toshifumi Hashimoto, Tianyu Tang, Tomofumi Fujimura, Ryo Fukuda, Jason Li, Hiroshi Maejima, Shintaro Hayashi, Akio Sugahara, Kei Akiyama, Koji Kato, Toru Miwa, Kensuke Yamamoto, Masahiro Yoshihara, Katsuaki Sakurai, Itaru Yamaguchi, Tsutomu Higuchi, Mizuki Kaneko, Jumpei Sato, Kazumasa Yamamoto, Yasuhiro Suematsu, Mitsuyuki Watanabe, Ryuji Yamashita, Venky Ramachandra, Kosuke Yanagidaira, Jiwang Lee, Kazuko Inuzuka, Hirotoshi Mori, Takatoshi Minamoto, Tomoharu Hashiguchi, Mitsuaki Honma, Juan Lee
Publikováno v:
ISSCC
This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density
Autor:
Hua-Ling Hsu, Hiromitsu Komai, Minoru Yamashita, Tai-yuan Tseng, Kapil Verma, Yasuyuki Kajitani, Hiroshi Nakamura, Venky Ramachandra, Jang Yong Kang, Pai K. Manjunath, Siddhesh Darne, Noboru Shibata, Jong Yuh, Chang Siau, Heguang Li, Raghavendra Rachineni, Toshiki Hisada, Katsuaki Isobe, Steve Choi, Toru Miwa, Takatoshi Minamoto, Naoya Tokiwa, Naoki Ookuma, Koichiro Hayashi, Alex Yap, Anirudh Amarnath, Susumu Ozawa, Masatoshi Okumura, Swaroop Kulkani, Stanley Jeong, Hitoshi Miwa, Tomoo Hishida, Jason Li, Pradeep Anantula, Masaki Unno, Hardwell Chibvongodze, Kazuaki Kawaguchi, Aki Matsuda, Ohwon Kwon, Masashi Yamaoka, Kwang-Ho Kim, Muralikrishna Balaga, Qui Nguyen, Takuya Ariki, Lei Lin, Anil Pai, Masahito Takehara, Ryo Fukuda, Mitsuyuki Watanabe, Srinivas Rajendra, Seungpil Lee, Yosuke Kato
Publikováno v:
ISSCC
Advancements in 3D-Flash memory-layer-stacking technology has enabled density scaling that circumvents the lithography limitations which have prevented 2D-NAND Flash memory from scaling [1]. Bit densities as high as 5.95Gb/mm2 on a single die were re