Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Shyam Pal"'
Publikováno v:
Chemical Society reviews. 46(16)
Continuous ongoing development of dense integrated circuits requires significant advancements in nanoscale patterning technology. As a key process in semiconductor high volume manufacturing (HVM), high resolution lithography is crucial in keeping wit
Autor:
Hiroto Nozawa, Frank W. Mont, Yuji Asakawa, Jongwook Kye, Taher Kagalwala, Kuniaki Takeda, Francis Goodwin, Tsunehito Kohyama, Xintuo Dai, Wenhui Wang, Lei Sun, Granger Lobb, Shyam Pal
Publikováno v:
SPIE Proceedings.
Optical metrology tool, LX530, is designed for high throughput and dense sampling metrology in semiconductor manufacture. It can inspect the dose and focus variation in the process control based on the critical dimension (CD) and line edge roughness
Publikováno v:
SPIE Proceedings.
Multiple patterning employing etch shrink extends the scaling of hardmask open CD (HCD) to sub-50nm regime. A plasma-assisted shrink technique is primarily used in the back-end-of-line (BEOL) however it faces major challenges such as the line end sho
Publikováno v:
2017 China Semiconductor Technology International Conference (CSTIC).
The rapid development in dense integrated circuits requires significant advancement in small scaling patterning technology. EUV technology is considered as a powerful solution for the sub-7 nm node pattering and beyond. The high performance resist de
Autor:
Aleksandra Clancy, Ayman Hamouda, Ashwini Chandrasekhar, Shyam Pal, Jeff Shu, Christopher Ordonio, Jason Eugene Stephens, Chun Hui Low, Ming He, Prakash Periasamy, Mary Claire Silvestre, Anbu Selvam Km Mahalingam, Peter Welti, Craig Child, Granger Lobb, Ketan Shah
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates
Autor:
Craig Child, Prakash Periasamy, Ashwini Chandrasekhar, Shyam Pal, Chun Hui Low, Anbu Selvam Km Mahalingam, Ketan Shah, Christopher Ordonio, Peter Welti
Publikováno v:
2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple patterning (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. In this paper, we demonstrate metal cr
Autor:
Yayi Wei, Sheldon Meyers, Sam Lee, Bumhwan Jeon, Chen Li, Sohan Singh Mehta, Lokesh Subramany, Shyam Pal, David Cho
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXVIII.
The NTD (Negative Tone Developer) process has been embraced as a viable alternative to traditionally, more conventional, positive tone develop processes. Advanced technology nodes have necessitated the adopting of NTD processes to achieve such tight
Autor:
Yun Tao Jiang, Mark Yelverton, Shyam Pal, Subramany Lokesh, Yayi Wei, Bumhwan Jeon, Sohan Singh Mehta, Chen Li
Publikováno v:
SPIE Proceedings.
Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignm
Autor:
Jean Raymond Fakhoury, Salman Iqbal, Shyam Pal, Craig Higgins, Hui Peng Koh, Shaowen Gao, Chris Karanikas, Bumhwan Jeon, Vikrant Chauhan, Lokesh Subramany, Pedro Morrison, Sohan Singh Mehta, David Cho, Yayi Wei
Publikováno v:
SPIE Proceedings.
The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to d
Autor:
Shyam Pal, Hui Husan Tsai, Michael D. Anderson, Wontae Hwang, Chien-Hsien S. Lee, Matthew Herrick, Xiang Hu, Yayi Wei, Bumhwan Jeon, Sohan Singh Mehta
Publikováno v:
SPIE Proceedings.
Higher density on 20nm logic chips require tighter pitches to be implemented not only at critical metal layers, but at BEOL critical VIA layers as well. Smaller pitches on critical via are no longer achievable through the conventional positive tone d