Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Shuso Fujii"'
Autor:
Daisaburo Takashima, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii, Mitsuhiro Noguchi
Publikováno v:
ISSCC
An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This embedded DRAM without extra costly manufacturing process realizes 2.4 mm2 /Mb macro density and provides large-capacity on-chip page buffers an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc97836aca2aa1ae6eb5a5faf7402f1f
https://doi.org/10.1109/jssc.2011.2170779
https://doi.org/10.1109/jssc.2011.2170779
Autor:
Shuso Fujii, Daisaburo Takashima, Ryu Ogiwara, Daisuke Hashimoto, Akihiro Nitayama, Shinichiro Shiratake, Ryo Fukuda, Susumu Shuto, Yohji Watanabe, Hidehiro Shiga, Tohru Ozaki, Katsuhiko Hoya, Iwao Kunishima, Tadashi Miyakawa, Sumiko Doumae, Takeshi Hamamoto, Hiroyuki Kanaya, Ryosuke Takizawa, Koji Yamakawa
Publikováno v:
ISSCC
A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 μm2 cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5daa454ca9ff7463fb3e94791bd14491
https://doi.org/10.1109/jssc.2011.2159053
https://doi.org/10.1109/jssc.2011.2159053
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:530-536
This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, an array architecture and data path design of 128 Mb chain FeRAM to meet HDD specifications, and a total power supply system for HDD applicat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a1f3ee5119d175ad34b8ffe23af3adb
https://doi.org/10.1109/jssc.2010.2091324
https://doi.org/10.1109/jssc.2010.2091324
Autor:
Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda
Publikováno v:
ISSCC
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fda70ed57de6c8e43a679a78faba8b0
https://doi.org/10.1109/jssc.2009.2034414
https://doi.org/10.1109/jssc.2009.2034414
Autor:
Tomoki Higashi, Kosuke Hatsuda, Tomoaki Shino, Takeshi Hamamoto, Tohru Furuyama, Yoshihiro Minami, Katsuyuki Fujita, Hiroomi Nakajima, Shuso Fujii, Shigeyoshi Watanabe, Takashi Ohsawa, Mutsuo Morikado, K. Inoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:135-145
A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arran
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7bdf900e64f47739a240c54a25a8b70f
https://doi.org/10.1109/jssc.0051.859018
https://doi.org/10.1109/jssc.0051.859018
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference.
This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, the 128Mb ChainFeRAMTM design and power supply system design to meet HDD application are presented. Second, the concept of nonvolatile FeRAM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70e1cedcdc9ea32b06b4210080459f3a
https://doi.org/10.1109/asscc.2009.5357235
https://doi.org/10.1109/asscc.2009.5357235
Publikováno v:
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
A single mask set DRAM architecture with a 1MW×1b or 256KW×4b organization, selectable by bonding configurations, will be discussed. With a CMOS half V cc cc generator, a standby current of 50μA has been achieved. A triple layer polysilicon N-well
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d4ad8e458ff214442d7ecac4e7cc021
https://doi.org/10.1109/isscc.1986.1156942
https://doi.org/10.1109/isscc.1986.1156942
Autor:
K. Natori, Shizuo Sawada, Shozo Saito, Shuso Fujii, Y. Okada, S. Shinozaki, M. Sato, O. Ozawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 21:643-648
A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access tim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9dd7cb82ac838f797c688f504566f02e
https://doi.org/10.1109/jssc.1986.1052589
https://doi.org/10.1109/jssc.1986.1052589
Publikováno v:
IEEE Journal of Solid-State Circuits. 20:903-908
A 1-Mb words/spl times/1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology is described. More than 2.2 million devices are integrated on a 62.5 mm/SUP 2/ silicon chip by utilizing an n-channel memory cell of triple-level poly Si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b0acabb61fee1bb79fc908b54fd68723
https://doi.org/10.1109/jssc.1985.1052413
https://doi.org/10.1109/jssc.1985.1052413
Publikováno v:
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ea81c1d7d116212faf159453cd025e6
https://doi.org/10.1109/isscc.1985.1156776
https://doi.org/10.1109/isscc.1985.1156776