Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Shuou Nomura"'
Autor:
Tomoya Suzuki, Kazuhiro Hiwada, Shintaro Sano, Shuou Nomura, Hirotsugu Kajihara, Tatsuo Shiozawa
Publikováno v:
Proceedings of the VLDB Endowment. 14:1311-1324
For applications in which small-sized random accesses frequently occur for datasets that exceed DRAM capacity, placing the datasets on SSD can result in poor application performance. For the read-intensive case we focus on in this paper, low latency
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::761c2590b86b2d119e1809cfddfee0d2
https://doi.org/10.14778/3457390.3457397
https://doi.org/10.14778/3457390.3457397
Autor:
Karthikeyan Sankaralingam, Shuou Nomura, Venkatraman Govindaraju, Marc de Kruijf, Matthew D. Sinclair, Chen-Han Ho
Publikováno v:
ISCA
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting and isolating faulty cores, but the required fault detection coverage beco
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5bd8b970753304abd86c33aa001da711
https://doi.org/10.1145/2000064.2000089
https://doi.org/10.1145/2000064.2000089
Publikováno v:
ISCA
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whether exposing hardware fault information to software and allowing softw
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c36bafd94003fa14157037083159048e
https://doi.org/10.1145/1815961.1816026
https://doi.org/10.1145/1815961.1816026
Publikováno v:
DSN
Due to fundamental device properties, energy efficiency from CMOS scaling is showing diminishing improvements. To overcome the energy efficiency challenges, timing speculation has been proposed to optimize for common-case timing conditions, with erro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::812c5458304d6a9987e7e1945ae09409
https://doi.org/10.1109/dsn.2010.5544278
https://doi.org/10.1109/dsn.2010.5544278
Autor:
T. Fujita, Fumiyuki Yamane, Hiroyuki Usui, Hiroyuki Hara, Fumihiko Tachibana, Takahiro Yamashita, Mototsugu Hamada, Yoshiro Tsuboi, Shuou Nomura, Yukimasa Miyamoto, Chen Kong Teh
Publikováno v:
2009 IEEE International Conference on IC Design and Technology.
A multi-core co-processor for mobile application processors is introduced. It provides low-power, high-throughput, fully software-based acceleration of multimedia processing. The test chip fabricated in a 65nm CMOS technology consumes 620mW in H.264
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45c7b90175cb035aa29e536e8b4dcbdc
https://doi.org/10.1109/icicdt.2009.5166280
https://doi.org/10.1109/icicdt.2009.5166280
Autor:
H. Sato, Takahiro Yamashita, S. Matsumoto, Fumiyuki Yamane, Yoshiro Tsuboi, Yohji Watanabe, Hiroyuki Hara, Fumihiko Tachibana, K. Seki, M. Hamada, Shuou Nomura, Takeshi Kitahara
Publikováno v:
CICC
A cell-based forward body-biasing technique to suppress the global process variation and its design flow are proposed. Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2 V with sma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dcf798b574b2451135cc8a4aa486c481
https://doi.org/10.1109/cicc.2008.4672012
https://doi.org/10.1109/cicc.2008.4672012
Autor:
Takashi Miyamori, K. Seki, Masato Uchiyama, S. Matsumoto, Fumiyuki Yamane, Yohji Watanabe, C. Kumtornkittikul, Jun Tanabe, M. Takahashi, Shuou Nomura, Hiroyuki Usui, Takahiro Yamashita, H. Sato, Y. Homma, Takeshi Kitahara, Yoshiro Tsuboi, Fumihiko Tachibana, M. Hamada, Yukimasa Miyamoto, Chen Kong Teh, Hiroyuki Hara, T. Fujita
Publikováno v:
ISSCC
A AAC-decoding, H.264 decoding, media processor with embedded forward-body-biasing and power-gating circuit in CMOS technology is proposed. Since all the components necessary for the scheme are simple MOS circuits requiring no extra supply voltages,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aae9232d7ca5af740a1278a72b209f40
https://doi.org/10.1109/isscc.2008.4523157
https://doi.org/10.1109/isscc.2008.4523157