Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Shun-Hsiang Chuang"'
Autor:
Shun-Hsiang Chuang, 莊舜翔
100
Power consumption is an essential concern in modern circuit designs. Clock gating, an efficient technique for power reduction, has been widely used. The basic structure of a circuit using clock gating could generally be classified into three
Power consumption is an essential concern in modern circuit designs. Clock gating, an efficient technique for power reduction, has been widely used. The basic structure of a circuit using clock gating could generally be classified into three
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/79977161425916600943
Autor:
Shun-Hsiang Chuang, 莊舜翔
97
This research apply Analysis Network Process (ANP) to collect experts’ judgments on forecasting sales volume of printer in Taiwan through pairwise comparison. When lacking of history data and clarity of social impacts, ANP technique can be
This research apply Analysis Network Process (ANP) to collect experts’ judgments on forecasting sales volume of printer in Taiwan through pairwise comparison. When lacking of history data and clarity of social impacts, ANP technique can be
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/56160339024789174987
Autor:
Chun-Chia Chen, Tsu-Ming Liu, Min-Hao Chiu, Tung-Hsing Wu, Chi-cheng Ju, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Peng-Hao Wang, Yen-Chao Huang, Chih-Ming Wang, Ping Chao, Hsiu-Yi Lin, Ming-Long Wu, Meng-Jye Hu, Yu-Kun Lin, Ting-An Lin, Chia-Yun Cheng, Che-Hong Chen, Sheng-Jen Wang, Shun-Hsiang Chuang, Han-Liang Chou, Chen Lien-Fei, Hue-Min Lin, Yung-Chang Chang, Chih-Da Chien, Kun-bin Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:56-67
A 4 K $\,\times\,$ 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 $\,\times\,$ 1.45 mm $^{2}$ die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content fe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4237a07f3493efd5831e6195d5e3fa3a
https://doi.org/10.1109/jssc.2015.2465857
https://doi.org/10.1109/jssc.2015.2465857
Autor:
Hsiao-En Chen, Ping Chao, Min-Hao Chiu, Hue-Min Lin, Chen Yi-Chang, Hsiu-Yi Lin, Chih-Wen Yang, Yung-Chang Chang, Shun-Hsiang Chuang, Meng-Jye Hu, Chi-cheng Ju, Chia-Yun Cheng, Fu-Chun Yeh, Che-Hong Chen, Peng Hsuan-Wen, Sheng-Jen Wang, Yenchieh Huang, Chun-Chia Chen, Chih-Ming Wang, Ming-Long Wu, Kao Chia-Hung, Tsu-Ming Liu, Chia-Lin Ho
Publikováno v:
ESSCIRC
A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7893b0820d5c8154d5276c1b46d73542
https://doi.org/10.1109/esscirc.2016.7598254
https://doi.org/10.1109/esscirc.2016.7598254
Autor:
Chia-Lin Ho, Ping Chao, Hsiu-Yi Lin, Che-Hong Chen, Min-Hao Chiu, Hue-Min Lin, Chun-Chia Chen, Ming-Long Wu, Tsu-Ming Liu, Chia-Yun Cheng, Fu-Chun Yeh, Shun-Hsiang Chuang, Chi-cheng Ju, Chih-Ming Wang, Yung-Chang Chang, Sheng-Jen Wang, Meng-Jye Hu
Publikováno v:
ICME
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external dat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b78113c8934404e0f385c47dce568209
https://doi.org/10.1109/icme.2015.7177399
https://doi.org/10.1109/icme.2015.7177399
Autor:
Min-Hao Chiu, Yu-Kun Lin, Peng-Hao Wang, Tsu-Ming Liu, Yen-Chao Huang, Ping Chao, Kun-bin Lee, Han-Liang Chou, Hue-Min Lin, Chen Lien-Fei, Ryan Chen, Yung-Chang Chang, Ming-Long Wu, Kevin Jou, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Che-Hong Chen, Tung-Hsing Wu, H Y Hsu, Sheng-Jen Wang, Chih-Da Chien, Ting-An Lin, Shun-Hsiang Chuang, Chun-Chia Chen, Chi-cheng Ju, Hsiu-Yi Lin, Chin-Ming Wang, Meng-Jye Hu, Chia-Yun Cheng, Fu-Chun Yeh
Publikováno v:
ISSCC
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::220b21ba0bbb83d403b694f7b2e5d1cb
https://doi.org/10.1109/isscc.2015.7063063
https://doi.org/10.1109/isscc.2015.7063063
Autor:
Min-Hao Chiu, Hsiu-Yi Lin, Che-Hong Chen, Chung-Hung Tsai, Chi-cheng Ju, Chia-Yun Cheng, Fu-Chun Yeh, Ping Chao, Tsu-Ming Liu, Chun-Chia Chen, Shun-Hsiang Chuang, Hue-Min Lin, Meng-Jye Hu, Chih-Ming Wang, Yung-Chang Chang, Ming-Long Wu, Sheng-Jen Wang
Publikováno v:
ESSCIRC
a first-reported 4Kx2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54825c0c372422eeff6298bd26e53f2a
https://doi.org/10.1109/esscirc.2014.6942055
https://doi.org/10.1109/esscirc.2014.6942055
Publikováno v:
Computers & Mathematics with Applications. (6):1545-1556
This study applies the Analytic Network Process (ANP) to forecast the sales volume of printers in Taiwan for adjusting the recycling and treatment fee as an incentive for recycling industries. When historical data are lacking and when a broad spectru
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fc5ffa9d893c6f97ee1d8de7cd5eb2a2