Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Shulang Ma"'
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 9, Pp 1188-1193 (2021)
In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D wi
Externí odkaz:
https://doaj.org/article/a7d3c702424e4ed88f01ea6201480c00
Autor:
Shulang Ma, Ran Ye, Siyang Liu, Hongting Chen, Yuwei Liu, Haibo Wu, Li Lu, Weifeng Sun, Wei Su, Wangran Wu, He Boyong
Publikováno v:
IEEE Transactions on Electron Devices. 67:1090-1097
Because of the extremely narrow dc thermal safe operating area for 700-V high-voltage lateral double-diffused MOS (LDMOS) transistor, the gate duty-cycle-accelerated ac stress was adopted to investigate its hot-carrier-induced degradations. It is fou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aab257e15a00c6503075c49d15aa35af
https://doi.org/10.1109/ted.2020.2967349
https://doi.org/10.1109/ted.2020.2967349
Autor:
Shulang Ma, Siyang Liu, Ran Ye, Zhibo Yin, Yuanchang Sang, Weifeng Sun, Li Lu, Feng Lin, Yuwei Liu, Wei Su
Publikováno v:
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).
In this work, four LDMOS devices with different split-STI structures (Device A: Ldmos with traditional split-STI, Device B: Ldmos with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and investigated. Because the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c4db068870f511758c309b1618effb18
https://doi.org/10.1109/edtm50988.2021.9420919
https://doi.org/10.1109/edtm50988.2021.9420919
Autor:
Ran Ye, Xue Ying, Siyang Liu, Shulang Ma, Weifeng Sun, Ye Tian, Wei Su, Yuwei Liu, Guipeng Sun, Feng Lin
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 18:284-290
The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::849c6336322096a8657d62c12f1a4b9d
https://doi.org/10.1109/tdmr.2018.2829550
https://doi.org/10.1109/tdmr.2018.2829550
Autor:
Sheng Li, Li Zhichao, Feng Lin, Yuwei Liu, Weifeng Sun, Siyang Liu, Wei Su, Shulang Ma, Guipeng Sun
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 17:780-784
Maximum operating gate voltage ( ${\mathbf{V}}_{\mathbf{gmax}} $ ) stress is observed and confirmed as the worst hot-carrier degradation condition for the lateral double-diffused MOS (LDMOS) with multiple floating poly-gate field plates. To reduce th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e90ab7625cf7e5531ea5d7f2308d45e0
https://doi.org/10.1109/tdmr.2017.2765687
https://doi.org/10.1109/tdmr.2017.2765687
Autor:
Fang Yunchao, Guipeng Sun, Weifeng Sun, Feng Lin, Yuwei Liu, Shulang Ma, Ren Xiaofei, Siyang Liu, Wei Su
Publikováno v:
IEEE Transactions on Electron Devices. 64:3275-3281
The electrical parameters degradations of lateral double-diffused MOS with multiple floating poly-gate field plates under different stress conditions have been investigated experimentally. For the maximum substrate current ( ${I}_{{\text {submax}}})$
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef5ad6ad15f4c6f2b98b23b42e268730
https://doi.org/10.1109/ted.2017.2711276
https://doi.org/10.1109/ted.2017.2711276
Publikováno v:
IEEE Transactions on Electron Devices. 63:1644-1649
The electrical parameters degradations for the lateral insulated gate bipolar transistor on a silicon-on-insulator substrate (SOI-LIGBT) under repetitive unclamped inductive switching (UIS) conditions have been experimentally investigated using the p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::850ef539545ed7eb4d2a2ed9005b005f
https://doi.org/10.1109/ted.2016.2535220
https://doi.org/10.1109/ted.2016.2535220
Publikováno v:
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD).
Due to serious self-heating effect, traditional DC stress is hard to be used for evaluating the hot-carrier degradation of the LDMOS above 600V. In this work, the hot-carrier degradation for a 724V-breakdown LDMOS is studied by adopting gate duty-cyc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d566156dc4829db1a6260856bbecd9d
https://doi.org/10.1109/ispsd.2018.8393667
https://doi.org/10.1109/ispsd.2018.8393667
Autor:
Siyang Liu, Feng Lin, Chunwei Zhang, Kaikai Xu, Jiaxing Wei, Wei Su, Ran Ye, Shulang Ma, Guipeng Sun, Weifeng Sun, Aijun Zhang
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 16:266-268
In this letter, a novel high latch-up immunity electrostatic discharge protection device that can be equivalent to a PNP-type bipolar junction transistor (BJT) and a series-connected Zener diode is proposed. For the proposed device, the emitter of it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84cde24237c2b7b5d4ef381278350328
https://doi.org/10.1109/tdmr.2016.2544350
https://doi.org/10.1109/tdmr.2016.2544350
Autor:
Siyang Liu, Bo Hou, Yuwei Liu, Chen Xin, Jiaxing Wei, Shulang Ma, Feng Lin, Ran Ye, Wei Su, Weifeng Sun, Haiyang Song
Publikováno v:
2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD).
In this work, a useful interfacial damage extraction method for SiC power MOSFETs based on the C-V characteristics is proposed. According to the five different interface situations of the channel region and the JFET region, the Cg-Vg curve can be div
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9b9d5c80b9b49f9ad3624ea9a531da5
https://doi.org/10.23919/ispsd.2017.7988992
https://doi.org/10.23919/ispsd.2017.7988992