Výsledky vyhledávání - "Shuangnan Liu"

Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows

Autor: Francis C. M. Lau, Benjamin Carrion Schafer, Shuangnan Liu

Publikováno v: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:2615-2627

In this article, we introduce an automatic stream computing reoptimization flow from ASICs to field-programmable gate arrays (FPGAs). Complex VLSI designs need to be prototyped and/or emulated on FPGAs. The main problem that we address in this articl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5c55006d066925b93e17b14cd524c115
https://doi.org/10.1109/tcad.2020.2966447

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Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration

Autor: Francis Cm Lau, Shuangnan Liu, Benjamin Carrion Schafer

Publikováno v: DAC

One of the advantages of High-Level Synthesis (HLS), also called C-based VLSI-design, over traditional RT-level VLSI design flows, is that multiple micro-architectures of unique area vs. performance can be automatically generated by setting different

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::49c26d65e1c98bd8a03420ea5ee81b09
https://doi.org/10.1145/3316781.3317754

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Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators

Autor: Felix Moreno, Monica Villaverde, Anushree Mahapatra, Siyuan Xu, Shuangnan Liu, Yidi Liu, Benjamin Carrion Schafer

Publikováno v: Microprocessors and Microsystems, ISSN 0141-9331, 2019-03, Vol. 65
Archivo Digital UPM
Universidad Politécnica de Madrid

This work proposes three different methods to automatically characterize heterogeneous MPSoCs composed of a variable number of masters (in the form of processors) and hardware accelerators (HWaccs). These hardware accelerators are given as Behavioral

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::17c9e753ee8888ff1ca9d691c47e9dcd
https://oa.upm.es/66874/

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Learning-based interconnect-aware dataflow accelerator optimization

Autor: Benjamin Carrion Schafer, Shuangnan Liu

Publikováno v: FPL

The interconnect is the Achilles heel of FPGAs. It currently dominates the delay and leads to high power consumption. It is thus, imperative to take it into account when designing complex FPGA systems. In this work, we propose a learning-based method

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::794d41d6b8fde1d7b18ce19e9329f857
https://doi.org/10.23919/fpl.2017.8056821

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Conference

Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration.

Autor: Shuangnan Liu, Lau, Francis C. M., Carrion Schafer, Benjamin

Publikováno v: DAC: Annual ACM/IEEE Design Automation Conference; 2019, Issue 56, p103-108, 6p

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